Wide bandwidth envelope trackers with reduced switching frequency for RF power amplifier

El requerimiento de proveer alta frecuencia de datos en los modernos sistema de comunicación inalámbricos resulta en complejas señales moduladas de radio-frequencia (RF) con un gran ancho de banda y alto ratio pico-promedio (PAPR). Para garantizar la linealidad del comportamiento, los amplificadores lineales de potencia comunes funcionan típicamente entre 4 y 10 dB de back-o_ desde la máxima potencia de salida, ocasionando una baja eficiencia del sistema. La eliminación y restauración de la evolvente (EER) y el seguimiento de la evolvente (ET) son dos prometedoras técnicas para resolver el problema de la eficiencia. Tanto en EER como en ET, es complicado diseñar un amplificador de potencia que sea eficiente para señales de RF de alto ancho de banda y alto PAPR. Una propuesta común para los amplificadores de potencia es incluir un convertidor de potencia de muy alta eficiencia operando a frecuencias más altas que el ancho de banda de la señal RF. En este caso, la potencia perdida del convertidor ocasionado por la alta frecuencia desaconseja su práctica cuando el ancho de banda es muy alto. La solución a este problema es el enfoque de esta disertación que presenta dos arquitecturas de amplificador evolvente: convertidor híbrido-serie con una técnica de evolvente lenta y un convertidor multinivel basado en un convertidor reductor multifase con control de tiempo mínimo. En la primera arquitectura, una topología híbrida está compuesta de una convertidor reductor conmutado y un regulador lineal en serie que trabajan juntos para ajustar la tensión de salida para seguir a la evolvente con precisión. Un algoritmo de generación de una evolvente lenta crea una forma de onda con una pendiente limitada que es menor que la pendiente máxima de la evolvente original. La salida del convertidor reductor sigue esa forma de onda en vez de la evolvente original usando una menor frecuencia de conmutación, porque la forma de onda no sólo tiene una pendiente reducida sino también un menor ancho de banda. De esta forma, el regulador lineal se usa para filtrar la forma de onda tiene una pérdida de potencia adicional. Dependiendo de cuánto se puede reducir la pendiente de la evolvente para producir la forma de onda, existe un trade-off entre la pérdida de potencia del convertidor reductor relacionada con la frecuencia de conmutación y el regulador lineal. El punto óptimo referido a la menor pérdida de potencia total del amplificador de evolvente es capaz de identificarse con la ayuda de modelo preciso de pérdidas que es una combinación de modelos comportamentales y analíticos de pérdidas. Además, se analiza el efecto en la respuesta del filtro de salida del convertidor reductor. Un filtro de dampeo paralelo extra es necesario para eliminar la oscilación resonante del filtro de salida porque el convertidor reductor opera en lazo abierto. La segunda arquitectura es un amplificador de evolvente de seguimiento de tensión multinivel. Al contrario que los convertidores que usan multi-fuentes, un convertidor reductor multifase se emplea para generar la tensión multinivel. En régimen permanente, el convertidor reductor opera en puntos del ciclo de trabajo con cancelación completa del rizado. El número de niveles de tensión es igual al número de fases de acuerdo a las características del entrelazamiento del convertidor reductor. En la transición, un control de tiempo mínimo (MTC) para convertidores multifase es novedosamente propuesto y desarrollado para cambiar la tensión de salida del convertidor reductor entre diferentes niveles. A diferencia de controles convencionales de tiempo mínimo para convertidores multifase con inductancia equivalente, el propuesto MTC considera el rizado de corriente por cada fase basado en un desfase fijo que resulta en diferentes esquemas de control entre las fases. La ventaja de este control es que todas las corrientes vuelven a su fase en régimen permanente después de la transición para que la siguiente transición pueda empezar muy pronto, lo que es muy favorable para la aplicación de seguimiento de tensión multinivel. Además, el control es independiente de la carga y no es afectado por corrientes de fase desbalanceadas. Al igual que en la primera arquitectura, hay una etapa lineal con la misma función, conectada en serie con el convertidor reductor multifase. Dado que tanto el régimen permanente como el estado de transición del convertidor no están fuertemente relacionados con la frecuencia de conmutación, la frecuencia de conmutación puede ser reducida para el alto ancho de banda de la evolvente, la cual es la principal consideración de esta arquitectura. La optimización de la segunda arquitectura para más alto anchos de banda de la evolvente es presentada incluyendo el diseño del filtro de salida, la frecuencia de conmutación y el número de fases. El área de diseño del filtro está restringido por la transición rápida y el mínimo pulso del hardware. La rápida transición necesita un filtro pequeño pero la limitación del pulso mínimo del hardware lleva el diseño en el sentido contrario. La frecuencia de conmutación del convertidor afecta principalmente a la limitación del mínimo pulso y a las pérdidas de potencia. Con una menor frecuencia de conmutación, el ancho de pulso en la transición es más pequeño. El número de fases relativo a la aplicación específica puede ser optimizado en términos de la eficiencia global. Otro aspecto de la optimización es mejorar la estrategia de control. La transición permite seguir algunas partes de la evolvente que son más rápidas de lo que el hardware puede soportar al precio de complejidad. El nuevo método de sincronización de la transición incrementa la frecuencia de la transición, permitiendo que la tensión multinivel esté más cerca de la evolvente. Ambas estrategias permiten que el convertidor pueda seguir una evolvente con un ancho de banda más alto que la limitación de la etapa de potencia. El modelo de pérdidas del amplificador de evolvente se ha detallado y validado mediante medidas. El mecanismo de pérdidas de potencia del convertidor reductor tiene que incluir las transiciones en tiempo real, lo cual es diferente del clásico modelos de pérdidas de un convertidor reductor síncrono. Este modelo estima la eficiencia del sistema y juega un papel muy importante en el proceso de optimización. Finalmente, la segunda arquitectura del amplificador de evolvente se integra con el amplificador de clase F. La medida del sistema EER prueba el ahorro de energía con el amplificador de evolvente propuesto sin perjudicar la linealidad del sistema. ABSTRACT The requirement of delivering high data rates in modern wireless communication systems results in complex modulated RF signals with wide bandwidth and high peak-to-average ratio (PAPR). In order to guarantee the linearity performance, the conventional linear power amplifiers typically work at 4 to 10 dB back-off from the maximum output power, leading to low system efficiency. The envelope elimination and restoration (EER) and envelope tracking (ET) are two promising techniques to overcome the efficiency problem. In both EER and ET, it is challenging to design efficient envelope amplifier for wide bandwidth and high PAPR RF signals. An usual approach for envelope amplifier includes a high-efficiency switching power converter operating at a frequency higher than the RF signal's bandwidth. In this case, the power loss of converter caused by high switching operation becomes unbearable for system efficiency when signal bandwidth is very wide. The solution of this problem is the focus of this dissertation that presents two architectures of envelope amplifier: a hybrid series converter with slow-envelope technique and a multilevel converter based on a multiphase buck converter with the minimum time control. In the first architecture, a hybrid topology is composed of a switched buck converter and a linear regulator in series that work together to adjust the output voltage to track the envelope with accuracy. A slow envelope generation algorithm yields a waveform with limited slew rate that is lower than the maximum slew rate of the original envelope. The buck converter's output follows this waveform instead of the original envelope using lower switching frequency, because the waveform has not only reduced slew rate but also reduced bandwidth. In this way, the linear regulator used to filter the waveform has additional power loss. Depending on how much reduction of the slew rate of envelope in order to obtain that waveform, there is a trade-off between the power loss of buck converter related to the switching frequency and the power loss of linear regulator. The optimal point referring to the lowest total power loss of this envelope amplifier is identified with the help of a precise power loss model that is a combination of behavioral and analytic loss model. In addition, the output filter's effect on the response is analyzed. An extra parallel damping filter is needed to eliminate the resonant oscillation of output filter L and C, because the buck converter operates in open loop. The second architecture is a multilevel voltage tracking envelope amplifier. Unlike the converters using multi-sources, a multiphase buck converter is employed to generate the multilevel voltage. In the steady state, the buck converter operates at complete ripple cancellation points of duty cycle. The number of the voltage levels is equal to the number of phases according the characteristics of interleaved buck converter. In the transition, a minimum time control (MTC) for multiphase converter is originally proposed and developed for changing the output voltage of buck converter between different levels. As opposed to conventional minimum time control for multiphase converter with equivalent inductance, the proposed MTC considers the current ripple of each phase based on the fixed phase shift resulting in different control schemes among the phases. The advantage of this control is that all the phase current return to the steady state after the transition so that the next transition can be triggered very soon, which is very favorable for the application of multilevel voltage tracking. Besides, the control is independent on the load condition and not affected by the unbalance of phase current. Like the first architecture, there is also a linear stage with the same function, connected in series with the multiphase buck converter. Since both steady state and transition state of the converter are not strongly related to the switching frequency, it can be reduced for wide bandwidth envelope which is the main consideration of this architecture. The optimization of the second architecture for wider bandwidth envelope is presented including the output filter design, switching frequency and the number of phases. The filter design area is restrained by fast transition and the minimum pulse of hardware. The fast transition needs small filter but the minimum pulse of hardware limitation pushes the filter in opposite way. The converter switching frequency mainly affects the minimum pulse limitation and the power loss. With lower switching frequency, the pulse width in the transition is smaller. The number of phases related to specific application can be optimized in terms of overall efficiency. Another aspect of optimization is improving control strategy. Transition shift allows tracking some parts of envelope that are faster than the hardware can support at the price of complexity. The new transition synchronization method increases the frequency of transition, allowing the multilevel voltage to be closer to the envelope. Both control strategies push the converter to track wider bandwidth envelope than the limitation of power stage. The power loss model of envelope amplifier is detailed and validated by measurements. The power loss mechanism of buck converter has to include the transitions in real time operation, which is different from classical power loss model of synchronous buck converter. This model estimates the system efficiency and play a very important role in optimization process. Finally, the second envelope amplifier architecture is integrated with a Class F amplifier. EER system measurement proves the power saving with the proposed envelope amplifier without disrupting the linearity performance.

Effects of modern variable frequency drive on the reliability of an old crane induction motor

The work aims to analyze the possibilities of utilizing old crane driving AC induction motors in modern pulse-width-modulated variable frequency drives. Bearing currents and voltage stresses are the two main problems associated with modern IGBT inverters, and they may cause premature failure of an old induction motor. The origins of these two problems are studied. An analysis of the mechanism of bearing failure is proposed. Certain types of bearing currents are considered in detail. The most effective and economical means are chosen for bearing currents mitigation. Transient phenomena of cables and mechanism of over voltages occurring at motor terminals are studied in the work. The weakest places of the stator winding insulation system are shown and recommendations are given considering the mitigation of voltage stresses. Only the most appropriate and cost effective preventative methods are chosen for old motor drives. Rewinding of old motors is also considered.

Optimal inverter design for an induction machine using resonant frequency matching

The frequency responses of two 50 Hz and one 400 Hz induction machines have been measured experimentally over a frequency range of 1 kHz to 400 kHz. This study has shown that the stator impedances of the machines behave in a similar manner to a parallel resonant circuit, and hence have a resonant point at which the Input impedance of the machine is at a maximum. This maximum impedance point was found experimentally to be as low as 33 kHz, which is well within the switching frequency ranges of modern inverter drives. This paper investigates the possibility of exploiting the maximum impedance point of the machine, by taking it into consideration when designing an inverter, in order to minimize ripple currents due to the switching frequency. Minimization of the ripple currents would reduce torque pulsation and losses, increasing overall performance. A modified machine model was developed to take into account the resonant point, and this model was then simulated with an inverter to demonstrate the possible advantages of matching the inverter switching frequency to the resonant point. Finally, in order to experimentally verify the simulated results, a real inverter with a variable switching frequency was used to drive an induction machine. Experimental results are presented.

Effects of dense code-switching on executive control

Bilingualism is reported to re-structure executive control networks, but it remains unknown which aspects of the bilingual experience cause this modulation. This study explores the impact of three code-switching types on executive functions: (1) alternation of languages, (2) insertion of lexicon of one language into grammar of another, (3) dense code-switching with co-activation of lexicon and grammar. Current models hypothesise that they challenge different aspects of the executive system because they vary in the extent and scope of language separation. Two groups of German-English bilinguals differing in dense code-switching frequency participated in a flanker task under conditions varying in degree of trial-mixing and resulting demands to conflict-monitoring. Bilinguals engaging in more dense code-switching showed inhibitory advantages in the condition requiring most conflict-monitoring. Moreover, dense code-switching frequency correlated positively with monitoring skills. This suggests that the management of co-activated languages during dense code-switching engages conflict-monitoring and that the consolidation processes taking place within co-activated linguistic systems involve local inhibition. Code-switching types requiring greater degrees of language separation may involve more global forms of inhibition. This study shows that dense code-switching is a key experience shaping bilinguals’ executive functioning and highlights the importance of controlling for participants’ code-switching habits in bilingualism research.

A unity power factor multiple isolated outputs switching mode power supply using a single switch

The authors present an offline switching power supply with multiple isolated outputs and unity power factor with the use of only one power processing stage, based on the DC-DC SEPIC (single ended primary inductance converter) modulated by variable hysteresis current control. The principle of operation, the theoretical analysis, the design procedure, an example, and simulation results are presented. A laboratory prototype, rated at 160 W, operating at a maximum switching frequency of 100 kHz, with isolated outputs rated at +5 V/15 A -5 V/1 A, +12 V/6 A and -12 V/1 A, has been built given an input power factor near unity.

A DC-DC converter based on the three-state switching cell for high current and voltage step-down applications

This paper presents a pulsewidth modulation dc-dc nonisolated buck converter using the three-state switching cell, constituted by two active switches, two diodes, and two coupled inductors. Only part of the load power is processed by the active switches, reducing the peak current through the switches to half of the load current, as higher power levels can then be achieved by the proposed topology. The volume of reactive elements, i.e., inductors and capacitors, is also decreased since the ripple frequency of the output voltage is twice the switching frequency. Due to the intrinsic characteristics of the topology, total losses are distributed among all semiconductors. Another advantage of this converter is the reduced region for discontinuous conduction mode when compared to the conventional buck converter or, in other words, the operation range in continuous conduction mode is increased, as demonstrated by the static gain plot. The theoretical approach is detailed through qualitative and quantitative analyses by the application of the three-state switching cell to the buck converter operating in nonoverlapping mode $(D < 0.5)$. Besides, the mathematical analysis and development of an experimental prototype rated at 1 kW are carried out. The main experimental results are presented and adequately discussed to clearly identify its claimed advantages. © 1986-2012 IEEE.

Comparative analysis between overlapping and non-overlapping operation modes for the PWM buck converter using the three-state switching cell

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Comparison of V2IC control with voltage mode and current mode controls for high frequency (MHz) and very fast response applications

High switching frequencies (several MHz) allow the integration of low power DC/DC converters. Although, in theory, a high switching frequency would make possible to implement a conventional Voltage Mode control (VMC) or Peak Current Mode control (PCMC) with very high bandwidth, in practice, parasitic effects and robustness limits the applicability of these control techniques. This paper compares VMC and CMC techniques with the V2IC control. This control is based on two loops. The fast internal loop has information of the output capacitor current and the error voltage, providing fast dynamic response under load and voltage reference steps, while the slow external voltage loop provides accurate steady state regulation. This paper shows the fast dynamic response of the V2IC control under load and output voltage reference steps and its robustness operating with additional output capacitors added by the customer.

Application and modeling of GaN FET in 1MHz large signal bandwidth power supply for radio frequency power amplifier

In this paper, implementation and testing of non- commercial GaN HEMT in a simple buck converter for envelope amplifier in ET and EER transmission techn iques has been done. Comparing to the prototypes with commercially available EPC1014 and 1015 GaN HEMTs, experimentally demonstrated power supply provided better thermal management and increased the switching frequency up to 25MHz. 64QAM signal with 1MHz of large signal bandw idth and 10.5dB of Peak to Average Power Ratio was gener ated, using the switching frequency of 20MHz. The obtaine defficiency was 38% including the driving circuit an d the total losses breakdown showed that switching power losses in the HEMT are the dominant ones. In addition to this, some basic physical modeling has been done, in order to provide an insight on the correlation between the electrical characteristics of the GaN HEMT and physical design parameters. This is the first step in the optimization of the HEMT design for this particular application.

Dual Active Bridge based Battery Charger for Plug-in Hybrid Electric Vehicle with Charging Current Containing Low Frequency Ripple

High power density is strongly preferable for the on-board battery charger of Plug-in Hybrid Electric Vehicle (PHEV). Wide band gap devices, such as Gallium Nitride HEMTs are being explored to push to higher switching frequency and reduce passive component size. In this case, the bulk DC link capacitor of AC-DC Power Factor Correction (PFC) stage, which is usually necessary to store ripple power of two times the line frequency in a DC current charging system, becomes a major barrier on power density. If low frequency ripple is allowed in the battery, the DC link capacitance can be significantly reduced. This paper focuses on the operation of a battery charging system, which is comprised of one Full Bridge (FB) AC-DC stage and one Dual Active Bridge (DAB) DC-DC stage, with charging current containing low frequency ripple at two times line frequency, designated as sinusoidal charging. DAB operation under sinusoidal charging is investigated. Two types of control schemes are proposed and implemented in an experimental prototype. It is proved that closed loop current control is the better. Full system test including both FB AC-DC stage and DAB DC-DC stage verified the concept of sinusoidal charging, which may lead to potentially very high power density battery charger for PHEV.

High Frequency Class DE Converter Using a Multilayer Coreless PCB Transformer

In modern power electronics equipment, it is desirable to design a low profile, high power density, and fast dynamic response converter. Increases in switching frequency reduce the size of the passive components such as transformers, inductors, and capacitors which results in compact size and less requirement for the energy storage. In addition, the fast dynamic response can be achieved by operating at high frequency. However, achieving high frequency operation while keeping the efficiency high, requires new advanced devices, higher performance magnetic components, and new circuit topology. These are required to absorb and utilize the parasitic components and also to mitigate the frequency dependent losses including switching loss, gating loss, and magnetic loss. Required performance improvements can be achieved through the use of Radio Frequency (RF) design techniques. To reduce switching losses, resonant converter topologies like resonant RF amplifiers (inverters) combined with a rectifier are the effective solution to maintain high efficiency at high switching frequencies through using the techniques such as device parasitic absorption, Zero Voltage Switching (ZVS), Zero Current Switching (ZCS), and a resonant gating. Gallium Nitride (GaN) device technologies are being broadly used in RF amplifiers due to their lower on- resistance and device capacitances compared with silicon (Si) devices. Therefore, this kind of semiconductor is well suited for high frequency power converters. The major problems involved with high frequency magnetics are skin and proximity effects, increased core and copper losses, unbalanced magnetic flux distribution generating localized hot spots, and reduced coupling coefficient. In order to eliminate the magnetic core losses which play a crucial role at higher operating frequencies, a coreless PCB transformer can be used. Compared to the conventional wire-wound transformer, a planar PCB transformer in which the windings are laid on the Printed Board Circuit (PCB) has a low profile structure, excellent thermal characteristics, and ease of manufacturing. Therefore, the work in this thesis demonstrates the design and analysis of an isolated low profile class DE resonant converter operating at 10 MHz switching frequency with a nominal output of 150 W. The power stage consists of a class DE inverter using GaN devices along with a sinusoidal gate drive circuit on the primary side and a class DE rectifier on the secondary side. For obtaining the stringent height converter, isolation is provided by a 10-layered coreless PCB transformer of 1:20 turn’s ratio. It is designed and optimized using 3D Finite Element Method (FEM) tools and radio frequency (RF) circuit design software. Simulation and experimental results are presented for a 10-layered coreless PCB transformer operating in 10 MHz.

Digitally-implemented naturally sampled PWM suitable for multilevel converter control

For dynamic closed loop control of a multilevel converter with a low pulse number (ratio of switching frequency to synthesized fundamental), natural sampled pulse-width modulation (PWM) is the best form of modulation. Natural sampling does not introduce distortion or a delayed response to the modulating signal. However previous natural sampled PWM implementations have generally been analog. For a modular multilevel converter, a digital implementation has advantages of accuracy and flexibility. Re-sampled uniform PWM is a novel digital modulation technique which approaches the performance of natural PWM. Both hardware and software implementations for a five level multilevel converter phase are presented, demonstrating the improvement over uniform PWM.

Limiting Internal Supply Voltage Spikes in DC-DC Converters

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.

Fast optimum-predictive control and capacitor voltage balancing strategy for bipolar back-to-back NPC converters in high-voltage direct current transmission systems

Multilevel power converters have been introduced as the solution for high-power high-voltage switching applications where they have well-known advantages. Recently, full back-to-back connected multilevel neutral point diode clamped converters (NPC converter) have been used inhigh-voltage direct current (HVDC) transmission systems. Bipolar-connected back-to-back NPC converters have advantages in long-distance HVDCtransmission systems over the full back-to-back connection, but greater difficulty to balance the dc capacitor voltage divider on both sending and receiving end NPC converters. This study shows that power flow control and dc capacitor voltage balancing are feasible using fast optimum-predictive-based controllers in HVDC systems using bipolar back-to-back-connected five-level NPC multilevel converters. For both converter sides, the control strategytakes in account active and reactive power, which establishes ac grid currents in both ends, and guarantees the balancing of dc bus capacitor voltages inboth NPC converters. Additionally, the semiconductor switching frequency is minimised to reduce switching losses. The performance and robustness of the new fast predictive control strategy, and its capability to solve the DC capacitor voltage balancing problem of bipolar-connected back-to-back NPCconverters are evaluated.

HVDC transmission systems: Bipolar back-to-back diode clamped multilevel converter with fastoptimum-predictive control and capacitor balancing strategy

Voltage source multilevel power converter structures are being considered for high power high voltage applications where they have well known advantages. Recently, full back-to-back connected multilevel neutral diode clamped converters (NPC) have been used in high voltage direct current (HVDC) transmission systems. Bipolar back-to-back connection of NPCs have advantages in long distance HVDC transmission systems, but highly increased difficulties to balance the dc capacitor voltage dividers on both sending and receiving end NPCs. This paper proposes a fast optimum-predictive controller to balance the dc capacitor voltages and to control the power flow in a long distance HVDCsystem using bipolar back-to-back connected NPCs. For both converter sides, the control strategy considers active and reactive power to establish ac grid currents on sending and receiving ends, while guaranteeing the balancing of both NPC dc bus capacitor voltages. Furthermore, the fast predictivecontroller minimizes the semiconductor switching frequency to reduce global switching losses. The performance and robustness of the new fast predictive control strategy and the associated dc capacitors voltage balancing are evaluated. (C) 2011 Elsevier B.V. All rights reserved.