Between writing and type: the stencil letter

An exhibition of stencil letters from the 18th century to the present day. Co-curated by Eric Kindel and Fred Smeijers, the exhibition featured a wide selection of stencil letters in the context of historical artefacts, documents and ephemera, including stencil plates and stencilling devices, specimens and catalogues and patent inventions. The exhibition also introduced a series of new stencil fonts designed by Maurice Göldner, Pierre Pané-Farré and Fred Smeijers. The design of each font made reference to and was informed by the historical material.

Stencil work in America, 1850–1900

An overview of stencil work in American in the second half of the nineteenth century, which shows and discusses stencil plates, stencil-making equipment, catalogues and other ephemera, and patents. The article additionally identifies some of the prominent individuals and companies who produced the work, and locates references to stencils in contemporary literature, including in the writing of Mark Twain.

Stencil dies: new tools for an old trade

Traces the invention and development of stencil dies in the USA in the middle decades of the nineteenth century, focussing on the work of M. J. Metcalf, A. J. Fullam, and S. M. Spencer.

Paper-hanger's companion: comprising tools, pastes, preparatory work; selection and hanging of wall-papers; distemper painting and cornice-tinting; stencil work; replacing sash-cord and broken window-panes; and useful wrinkles and receipts.

Mode of access: Internet.

The Loop-of-Stencil-Reduce Paradigm

In this paper we advocate the Loop-of-stencil-reduce pattern as a way to simplify the parallel programming of heterogeneous platforms (multicore+GPUs). Loop-of-Stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop. It transparently targets (by using OpenCL) combinations of CPU cores and GPUs, and it makes it possible to simplify the deployment of a single stencil computation kernel on different GPUs. The paper discusses the implementation of Loop-of-stencil-reduce within the FastFlow parallel framework, considering a simple iterative data-parallel application as running example (Game of Life) and a highly effective parallel filter for visual data restoration to assess performance. Thanks to the high-level design of the Loop-of-stencil-reduce, it was possible to run the filter seamlessly on a multicore machine, on multi-GPUs, and on both.

A parallel pattern for iterative stencil + reduce

We advocate the Loop-of-stencil-reduce pattern as a means of simplifying the implementation of data-parallel programs on heterogeneous multi-core platforms. Loop-of-stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop in both data-parallel and streaming applications, or a combination of both. The pattern makes it possible to deploy a single stencil computation kernel on different GPUs. We discuss the implementation of Loop-of-stencil-reduce in FastFlow, a framework for the implementation of applications based on the parallel patterns. Experiments are presented to illustrate the use of Loop-of-stencil-reduce in developing data-parallel kernels running on heterogeneous systems.

A computational fluid dynamics study of the stencil printing process

Abstract not available

Coarse-grid higher order finite-difference time-domain algorithm with low dispersion errors

Higher order (2,4) FDTD schemes used for numerical solutions of Maxwell`s equations are focused on diminishing the truncation errors caused by the Taylor series expansion of the spatial derivatives. These schemes use a larger computational stencil, which generally makes use of the two constant coefficients, C-1 and C-2, for the four-point central-difference operators. In this paper we propose a novel way to diminish these truncation errors, in order to obtain more accurate numerical solutions of Maxwell`s equations. For such purpose, we present a method to individually optimize the pair of coefficients, C-1 and C-2, based on any desired grid size resolution and size of time step. Particularly, we are interested in using coarser grid discretizations to be able to simulate electrically large domains. The results of our optimization algorithm show a significant reduction in dispersion error and numerical anisotropy for all modeled grid size resolutions. Numerical simulations of free-space propagation verifies the very promising theoretical results. The model is also shown to perform well in more complex, realistic scenarios.

Comparison of fungal contamination between hospitals and companies food units

A descriptive study was developed to compare air and surfaces fungal contamination in ten hospitals’ food units and two food units from companies. Fifty air samples of 250 litres through impaction method were collected from hospitals’ food units and 41 swab samples from surfaces were also collected, using a 10 by 10 cm square stencil. Regarding the two companies, ten air samples and eight surface samples were collected. Air and surface samples were collected in food storage facilities, kitchen, food plating and canteen. Outdoor air was also collected since this is the place regarded as a reference. Simultaneously, temperature, relative humidity and meal numbers were registered. Concerning air from hospitals’ food units, 32 fungal species were identified, being the two most commonly isolated genera Penicillium sp.

Exposure to fungi in dockers

Several activities are ensured by dockers increase occupational exposure to several risk factors. being one of them the fungal burden from the load. In this study we aim at characterizing fungal contamination in one warehouse that storage sugar cane from a ship, and also in one crane cabinet that unload the same sugar cane from the ship. Air samples were collected from the warehouse and from inside the crane cabinet. An outdoor sample was also collected, from each sampling site, and regarding as reference. Sampling volume was selected depending in the contamination expected and the air samples were collect through an impaction method in a flow rate of 140 L/min onto malt extract agar (MEA) supplemented with chloramphenicol (0.05%), using the Millipore air Tester (Millipore). Surfaces samples from the warehouse were collected by swabbing the surfaces of the same indoor sites, using a 10 by 10cm square stencil according to the International Standard ISO 18593 (2004). The obtained swabs were then plated onto MEA. All the collected samples were incubated at 27ºC for 5 to 7 days. After laboratory processing and incubation of the collected samples, quantitative (colony-forming units - CFU/m3 and CFU/m2) and qualitative results were obtained with identification of the isolated fungal species. Aspergillus fumigatus present the highest fungal load and WHO guideline was overcome in both indoor sampling sites. The results obtained in this study highlight the need to know better the exposure burden from dockers, and specifically to fungi contamination.