Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

Shallow donor defect formation and its influence on semi-insulating indium phosphide after high temperature annealing with long duration

Fe-doped semi-insulating (SI) InP has become semi-conducting (SC) material completely after annealing at 900 V for 10 hours. Defects in the SC and SI InP materials have been studied by deep level transient spectroscopy (DLTS) and thermally stimulated current spectroscopy (TSC) respectively. The DLTS only detected Fe acceptor related deep level defect with significant concentration, suggesting the formation of a high concentration of shallow donor in the SC-InP TSC results confirmed the nonexistence of deep level defects in the annealed SI-InP. The results demonstrate a significant influence of the thermally induced defects on the electrical properties of SI-InP. The formation mechanism and the nature of the shallow donor defect have been discussed based on the results.

Molecular beam epitaxial growth of GaN on 3c-SiC/Si(111) substrates using a thick AIN buffer layer

Hexagonal GaN films (similar to 3 mu m) were grown on 3c-SiC/Si(111) and carbonized Si(111) substrates using a thick AlN buffer Cracks are observed on the surface of the GaN film grown on the carbonized Si(111), while no cracks are visible on the 3c-SiC/Si(111). XRD exhibits polycrystalline nature of the GaN film grown on the carbonized Si(111) due to poorer crystalline quality of this substrate. Raman spectra reveal that all GaN layers are under tensile stress, and the GaN layer grown on 3c-SiC/Si(111) shows a very low stress value of sigma(xx) = 0.65 Gpa. In low-temperature Photoluminescence spectra the remarkable donor-acceptor-pair recombination and yellow band can be attributed to the incorporation of Si impurities from the decomposition of SiC.

Growth and characterization of 4H-SiC by horizontal hot-wall CVD

4H-SiC layers have been homoepitaxially grown at 1500 degrees C with the use of a horizontal hot-wall chemical vapor deposition (CVD) system, which was built in the author's group. The typical growth rate was 2 mu m/h at a pressure of 40 Torr. The background donor concentration has been reduced to 2.3 x 10(15) cm(-3) during a prolonged growth run. It confirmed the idea that the high background concentration of thin films was caused by the impurities inside the susceptor and thermal insulator The FWHM of x-ray co-rocking curves show 9 similar to 15 aresecs in five different areas of a 32-mu m-thick 4H-SiC epilayer The free exciton peaks dominated in the near-band-edge low-temperature photoluminescence spectrum (LTPL), indicating high crystal quality.

Controlled growth of III-V compound semiconductor nano-structures and their application in quantum-devices

Various techniques on the growth of self-assembled compound semiconductor nano-structures (quantum dots, QDs) have been tried to enhance the controlling on size, density, emitting wavelength, uniformity in size and ordering in location of the QDs. Optimized growth conditions have been used in the application of the QD materials in opto-electronic devices. High-power long-lifetime quantum-dot laser-diodes (QD-LDs) emitting near 1 mu m, QD-LDs emitting in red-light range, 1.3 mu m QD-LDs on GaAs substrate and quantum-dot super-luminescent diodes (QD-SLDs) have successfully been achieved.

Molecular-beam epitaxial growth of position controlled InAs islands on cleaved edge of InGaAs/GaAs superlattice

A promising approach for positioning of InAs islands on (110)GaAs is demonstrated. By combining self-assembly of quantum dots with solid source molecular beam epitaxy (MBE) on cleaved edge of InGaAs/GaAs superlattice (SL), linear alignment of InAs islands on the InGaAs strain layers have been fabricated The cleaved edge of InGaAs/GaAs SL acts as strain nanopattern for InAs selective growth. Indium atoms incident on the surface will preferentially migrate to InGaAs regions where favorable bonding sites are available. The strain nanopattern's effect is studied by the different indium fraction and thickness of InxGa1-xAs/GaAs SL. The ordering of the InAs islands is found to depend on the properties of the underlying InGaAs strain layers.

Effect of noncoherent islands on the optical properties of the 1.3 mu m InAs/GaAs quantum dots during rapid thermal annealing

The effect of thermal annealing of InAs/GaAs quantum dots (QDs) with emission wavelength at 1.3 mu m have been investigated by photoluminescence (PL) and transmission electron microscopy (TEM measurements. There is a dramatic change in the A spectra when the annealing temperature is raised up to 800 degrees C: an accelerated blushifit of the main emission peak of QDs together with an inhomogeneous broadening of the linewidth. The TEM images shows that the lateral size of normal QDs decreases as the annealing temperature is increased, while the noncoherent islands increase their size and densit. A small fraction of the relative large QDs contain dislocations when the annealing temperature increases up to 800 degrees C. The latter leads to the strong decrease of the PL intensity.

Micro-fabricated Al0.3Ga0.7As pyramids for potential SPM applications

A novel technique of manufacturing Al0.3Ga0.7As pyramids by liquid phase epitaxy (LPE) for scanning probe microscopy (SPM) sensors is reported Four meticulously designed conditions-partial oxidation, deficient solute, air quenching and germanium doping result in defect-free homogeneous nucleation and subsequent pyramid formation. Micrometer-sized frustums and pyramids are detected by scanning electron microscopy (SEM). The sharp end of the microtip has a radius of curvature smaller than 50 nm. It is believed that such accomplishments would contribute not only to crystal growth theory, but also to miniature fabrication technology.

Raman scattering study on diluted magnetic semiconductor Ga1-xMnxAs prepared by Mn-ion implantation

Raman scattering measurements have been performed in diluted magnetic semiconductor Ga1-xMnxAs prepared by Mn-ion implantation, deposition, and post-annealing technique. It is found that the Raman spectrum measured from the implanted surface of the sample shows some new weak modes in addition to the GaAs-like modes which are observed from the unimplanted surface. The new vibrational modes observed are assigned to MnAs-like modes. The coupled LO-phonon plasmon mode, and Mn and As related vibrational modes caused by Mn-ion implantation, deposition, and post-annealing are also observed. Furthermore, the GaAs-like modes are found to be shifted by approximately 4 cm(-1) in the lower frequency side, compared with those observed from the unimplanted surface.

Edge dislocation of b=[001]/2 in the InAs nanostructure on InP(001)

The self-organized InAs/In0.52Al0.48As nanostructure were grown on InP (001) using molecular beam epitaxy (MBE). The nanostructure has been studied using transmission electron microscopy (TEM) and high resolution transmission electron microscopy (HRTEM). The edge dislocations with the Burgers vector b = ([001]/2) and extending along the [$(110) over bar $] direction are observed. The results show that in the region near an edge dislocation, no InAs wires were formed, while in the regions free of dislocation, wire-like nanostructures were formed. The mechanisms for the formation of the [001]/2 edge dislocations were discussed.

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

Estudio de prospectiva : Adornos FAMEGO al año 2015

El Almacén de Adornos FAMEGO, ubicado dentro del sector de San Victorino, el cual a través de los años se ha caracterizado por ser muy concurrente por las familias Colombianas de los estratos 1, 2 y 3, gracias a que su ubicación en el centro de la capital hace sea que el destino más próximo para aquellos consumidores finales de Adornos, que su principal objetivo es buscar el mejor precio en sus insumos para confección.Mediante el estudio prospectivo del Almacén FAMEGO, se analizaron características como: tendencias (Globalización, nuevos concepto del mercado, tasa de cambio), factores internos y externos (Precios, seguridad, población marginal), los cuales llevaron a generar hipótesis que mostraran los distintos escenarios del Almacén FAMEGO con un horizonte al año en el 2015. En el 2015, el sector de San Victorino, se vislumbra como un centro de negocios al aire libre, en el cual habrá un ambiente más confortable para todos los clientes, con mayor seguridad por parte de las autoridades y control en cuanto al desarrollo sostenible del sector, brindando adecuados niveles de limpieza en las calles y una menor contaminación visual. El almacén FAMEGO, caracterizado por brindar a sus clientes el mejor servicio, ha creado alianzas con sus principales competidores para crear un ambiente más sano en el mercado, estableciendo una equidad en los precios de los productos.

Identificación de escenarios a futuro para lograr competitividad en el sector de telefonía móvil en Colombia al año 2020

Este trabajo pretende explorar el desarrollo del sector de la telefonía móvil desde sus inicios hasta la actualidad en Colombia, con el fin de generar escenarios de futuro. Las herramientas prospectivas MicMac (Análisis Estructural Prospectivo), Smic (Sistema de Matrices de Impactos Cruzados) y la opinión de expertos líderes del sector, son la base principal para el desarrollo del trabajo. Las entidades gubernamentales, la CTR (Comisión de Regulación de Telecomunicaciones), y los líderes de los operadores del sector de telefonía móvil, entre otros, se han concientizado que la innovación es la base del éxito en este tipo de organizaciones y por eso se ha trabajado en mejorar su regulación, logrando de esta manera que el desarrollo de los productos y servicios que se ofrecen sean cada vez mejores y perjudique en menor medida al medio ambiente y a los usuarios. Este subsector de las telecomunicaciones, es el más dinámico y con mayor potencial. Sin embargo, este también es afectado por las condiciones económicas del mercado, la inestabilidad política, las importaciones y exportaciones derivadas de los tratados comerciales, entre otros temas. El escenario apuesta facilitaría la prestación de productos con tecnología de punta y servicios con la mejor cobertura y acceso posible a precios bajos.

Estado actual del sector estratégico hoteles boutique en Bogotá e identificación de los escenarios de desarrollo alternativos

En el presente trabajo se realizara la aplicación del modelo Análisis Estructural de los Sectores estratégicos y del análisis prospectivo para los hoteles que hacen parte del sector alojamiento en hoteles boutique en Bogotá en un periodo de cinco años. En estos modelos se tiene en cuenta la información financiera, interna y externa de la empresa y aspectos generales relacionados con la economía del sector. La investigación se desarrolló en dos etapas; la primera corresponde al desarrollo del AESE el cual se basa en cuatro herramientas (análisis de hacinamiento cuantitativo y cualitativo, levantamiento del panorama competitivo, análisis estructural de fuerzas del mercado y estudio de competidores) y el análisis prospectivo donde se aplica la metodología MICMAC, MACTOR y SMIC, en las cuales se determinan los escenarios alternativos teniendo presente la influencia que puedan tener los actores del sector y los aspectos sociales, políticos, tecnológicos y económicos en las definición de los escenarios.