Kapearailotekniikan käyttö jauhekaarihitsauksessa

Diplomityössä tavoitteena oli tutkia kapearailojauhekaaritekniikan soveltuvuutta konepajakäyttöön ja sen vaikutusta hitsauksen tuottavuuteen sekä hitsin mekaanisiin ominaisuuksiin. Työ tehtiin vertailukokeilla, jossa koehitsaukset suoritettiin eri aineenpaksuuksille siten, että jokaiselle tutkimuksen kohteena olleelle materiaalille tehtiin yksi hitsaus käytössä olevalla jauhekaaritekniikalla, jolloin saatiin vertailukohde, johon uutta kapearailotekniikkaa verrattiin. Tulokset osoittivat, että kapearailotekniikalla 1 palko/palkokerros aineenpaksuudeltaan Pl. 60 mm koekappale saatiin hitsattua n. 39 % nopeammin verrattuna perinteiseen tandem -hitsaukseen. Kyseisellä aineenpaksuudella lisäainelangan kulutus oli n. 41 % ja jauheen kulutus n. 71 % pienempi verrattuna perinteiseen X- railohitsaukseen tandem -menetelmällä. Lisäksi tuli esille, että ”palkoa palonpäälle” -tekniikka on kapearailotekniikoista tehokkain, sillä 2 palkoa/palkokerros menetelmässä railon leveyttä jouduttiin leventämään, jolloin kapearailotekniikan pieni railotilavuus menetettiin. Lisäaineen kulutus tälläkin menetelmällä jäi pienemmäksi verrattuna X- railohitsaukseen. Ennalta pelättyä kuonan irtoamisongelmaa ei kapearailohitsauksessa havaittu, vaan kuona irtosi ongelmitta railon kyljistä. Lisäksi kapearailotekniikalla hitsattujen hitsien lujuudet olivat vertailukelpoiset tandem- ja yksilankamenetelmällä hitsattujen hitsien kanssa.

Welding development of crane main girder

Konecranes Corporation manufactures huge steel structures in 16 factories worldwide, in which the environment and quality varies. The company has a desire to achieve the same weld quality in each factory, regardless of the manufacturing place. The main subject of this master’s thesis was to develop the present box girder crane welding process, submerged arc welding and especially the fillet welding. Throughput time and manufacturing costs can be decreased by welding the full penetration fillet weld without a bevel, changing present groove types for more appropriate ones and by achieving the desired weld quality on the first time. Welding experiments of longitudinal fillet welding were made according to the present challenges, which the manufacturing process is facing. In longitudinal fillet welding tests the main focus was to achieve full penetration fillet weld for 6, 8 and 10 millimeters thick web plates with single and twin wire submerged arc welding. Full penetration was achieved with all the material thicknesses, both with single and twin wire submerged arc welding processes. The main problem concerning the weld was undercutting and shape of the weld bead. The question about insufficiency of presently used power sources with twin wire was risen up during testing, due to the thicknesses that require high welding current. Bigger power source is required when box girders are welded nonstop, if twin wire is used. For single wire process the penetration was achieved with significantly less amperage than with twin wire.

Applications and Benefits of Adaptive Pulsed GMAW

In ship and offshore terminal construction, welded cross sections are thick and the number of welds very high. Consequently, there are two aspects of great importance; cost and heat input. Reduction in the welding operation time decreases the costs of the work force and avoids excessive heat, preventing distortion and other weld defects. The need to increase productivity while using a single wire in the GMAW process has led to the use of a high current and voltage to improve the melting rate. Unfortunately, this also increases the heat input. Innovative GMAW processes, mostly implemented for sheet plate sections, have shown significant reduction in heat input (Q), low distortion and increase in welding speed. The aim of this study is to investigate adaptive pulsed GMAW processes and assess relevant applications in the high power range, considering possible benefits when welding thicker sections and high yield strength steel. The study experimentally tests the usability of adaptive welding processes and evaluates their effects on weld properties, penetration and shapes of the weld bead.The study first briefly reviews adaptive GMAW to evaluate different approaches and their applications and to identify benefits in adaptive pulsed. Experiments are then performed using Synergic Pulsed GMAW, WiseFusionTM and Synergic GMAW processes to weld a T-joint in a horizontal position (PB). The air gap between the parts ranges from 0 to 2.5 mm. The base materials are structural steel grade S355MC and filler material G3Si1. The experiment investigates heat input, mechanical properties and microstructure of the welded joint. Analysis of the literature reveals that different approaches have been suggested using advanced digital power sources with accurate waveform, current, voltage, and feedback control. In addition, studies have clearly indicated the efficiency of lower energy welding processes. Interest in the high power range is growing and a number of different approaches have been suggested. The welding experiments in this study reveal a significant reduction of heat input and a weld microstructure with the presence of acicular ferrite (AF) beneficial for resistance to crack propagation. The WiseFusion bead had higher dilution, due to the weld bead shape, and low defects. Adaptive pulse GMAW processes can be a favoured choice when welding structures with many welded joints. The total heat reduction mitigates residual stresses and the bead shape allows a higher amperage limit. The stability of the arc during the process is virtually spatter free and allows an increase in welding speed.

Hybrid Multiferroic Nanostructure with Magnetic−Dielectric Coupling

The development of methods to economically synthesize single wire structured multiferroic systems with room temperature spin−charge coupling is expected to be important for building next-generation multifunctional devices with ultralow power consumption. We demonstrate the fabrication of a single nanowire multiferroic system, a new geometry, exhibiting room temperature magnetodielectric coupling. A coaxial nanotube/nanowire heterostructure of barium titanate (BaTiO3, BTO) and cobalt (Co) has been synthesized using a template-assisted method. Room temperature ferromagnetism and ferroelectricity were exhibited by this coaxial system, indicating the coexistence of more than one ferroic interaction in this composite system

Two Surgical Approaches to Fracture Malunion Repair

Two birds were presented with malunion fractures. The first was a young toco toucan (Ramphastos toco) with malunion of the tarsometatarsus that was treated by an opening-corrective osteotomy and an acrylic-pin external skeletal fixator (type II) to stabilize the osteotomy. The second bird was m adult southern caracara (Caracara plancus) with radial and ulnar malunion that was treated by closing-wedge osteotomies. Stabilization of the osteotomy sites was accomplished through 1 bone plate fixed cranially on the ulna with 6 cortical screws and an interfragmentary single wire in radius. In both cases, the malunion was corrected, but the manus of the southern caracara was amputated because of carpal joint luxation that induced malposition of the feathers.

Power flow in distribution networks with earth return

The problems of wave propagation and power flow in the distribution network composed of an overhead wire parallel to the surface of the ground have not been satisfactorily solved. While a complete solution of the actual problem is impossible, as it is explained in the famous Carson's paper (1926), the solution of the problem, where the actual earth is replaced by a plane homogenous semi-infinite solid, is of considerable interest. In this paper, a power flow algorithm in distribution networks with earth return, based on backward-forward technique, is discussed. In this novel use of the technique, the ground is explicitly represented. In addition, an iterative method for determining impedance for modelling ground effect in the extended power flow algorithm is suggested. Results obtained from single-wire and three-wire studies using IEEE test networks are presented and discussed. (C) 2003 Elsevier Ltd. All rights reserved.

Análise dos potenciais de superfície gerados no solo por um sistema monofilar com retorno por terra

Pós-graduação em Agronomia (Energia na Agricultura) - FCA

Analog Signal Acquisition and Conditioning for Near-Field Capacitive Communication and Active Combined EEG-EIT Monitoring

The work of the present thesis is focused on the implementation of microelectronic voltage sensing devices, with the purpose of transmitting and extracting analog information between devices of different nature at short distances or upon contact. Initally, chip-to-chip communication has been studied, and circuitry for 3D capacitive coupling has been implemented. Such circuits allow the communication between dies fabricated in different technologies. Due to their novelty, they are not standardized and currently not supported by standard CAD tools. In order to overcome such burden, a novel approach for the characterization of such communicating links has been proposed. This results in shorter design times and increased accuracy. Communication between an integrated circuit (IC) and a probe card has been extensively studied as well. Today wafer probing is a costly test procedure with many drawbacks, which could be overcome by a different communication approach such as capacitive coupling. For this reason wireless wafer probing has been investigated as an alternative approach to standard on-contact wafer probing. Interfaces between integrated circuits and biological systems have also been investigated. Active electrodes for simultaneous electroencephalography (EEG) and electrical impedance tomography (EIT) have been implemented for the first time in a 0.35 um process. Number of wires has been minimized by sharing the analog outputs and supply on a single wire, thus implementing electrodes that require only 4 wires for their operation. Minimization of wires reduces the cable weight and thus limits the patient's discomfort. The physical channel for communication between an IC and a biological medium is represented by the electrode itself. As this is a very crucial point for biopotential acquisitions, large efforts have been carried in order to investigate the different electrode technologies and geometries and an electromagnetic model is presented in order to characterize the properties of the electrode to skin interface.

A Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration

Current nanometer technologies suffer within-die parameter uncertainties, varying workload conditions, aging, and temperature effects that cause a serious reduction on yield and performance. In this scenario, monitoring, calibration, and dynamic adaptation become essential, demanding systems with a collection of multi purpose monitors and exposing the need for light-weight monitoring networks. This paper presents a new monitoring network paradigm able to perform an early prioritization of the information. This is achieved by the introduction of a new hierarchy level, the threshing level. Targeting it, we propose a time-domain signaling scheme over a single-wire that minimizes the network switching activity as well as the routing requirements. To validate our approach, we make a thorough analysis of the architectural trade-offs and expose two complete monitoring systems that suppose an area improvement of 40% and a power reduction of three orders of magnitude compared to previous works.

On-chip Monitoring: A Light-Weight Interconnection Network Approach

Current nanometer technologies are subjected to several adverse effects that seriously impact the yield and performance of integrated circuits. Such is the case of within-die parameters uncertainties, varying workload conditions, aging, temperature, etc. Monitoring, calibration and dynamic adaptation have appeared as promising solutions to these issues and many kinds of monitors have been presented recently. In this scenario, where systems with hundreds of monitors of different types have been proposed, the need for light-weight monitoring networks has become essential. In this work we present a light-weight network architecture based on digitization resource sharing of nodes that require a time-to-digital conversion. Our proposal employs a single wire interface, shared among all the nodes in the network, and quantizes the time domain to perform the access multiplexing and transmit the information. It supposes a 16% improvement in area and power consumption compared to traditional approaches.

On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors

La temperatura es una preocupación que juega un papel protagonista en el diseño de circuitos integrados modernos. El importante aumento de las densidades de potencia que conllevan las últimas generaciones tecnológicas ha producido la aparición de gradientes térmicos y puntos calientes durante el funcionamiento normal de los chips. La temperatura tiene un impacto negativo en varios parámetros del circuito integrado como el retardo de las puertas, los gastos de disipación de calor, la fiabilidad, el consumo de energía, etc. Con el fin de luchar contra estos efectos nocivos, la técnicas de gestión dinámica de la temperatura (DTM) adaptan el comportamiento del chip en función en la información que proporciona un sistema de monitorización que mide en tiempo de ejecución la información térmica de la superficie del dado. El campo de la monitorización de la temperatura en el chip ha llamado la atención de la comunidad científica en los últimos años y es el objeto de estudio de esta tesis. Esta tesis aborda la temática de control de la temperatura en el chip desde diferentes perspectivas y niveles, ofreciendo soluciones a algunos de los temas más importantes. Los niveles físico y circuital se cubren con el diseño y la caracterización de dos nuevos sensores de temperatura especialmente diseñados para los propósitos de las técnicas DTM. El primer sensor está basado en un mecanismo que obtiene un pulso de anchura variable dependiente de la relación de las corrientes de fuga con la temperatura. De manera resumida, se carga un nodo del circuito y posteriormente se deja flotando de tal manera que se descarga a través de las corrientes de fugas de un transistor; el tiempo de descarga del nodo es la anchura del pulso. Dado que la anchura del pulso muestra una dependencia exponencial con la temperatura, la conversión a una palabra digital se realiza por medio de un contador logarítmico que realiza tanto la conversión tiempo a digital como la linealización de la salida. La estructura resultante de esta combinación de elementos se implementa en una tecnología de 0,35 _m. El sensor ocupa un área muy reducida, 10.250 nm2, y consume muy poca energía, 1.05-65.5nW a 5 muestras/s, estas cifras superaron todos los trabajos previos en el momento en que se publicó por primera vez y en el momento de la publicación de esta tesis, superan a todas las implementaciones anteriores fabricadas en el mismo nodo tecnológico. En cuanto a la precisión, el sensor ofrece una buena linealidad, incluso sin calibrar; se obtiene un error 3_ de 1,97oC, adecuado para tratar con las aplicaciones de DTM. Como se ha explicado, el sensor es completamente compatible con los procesos de fabricación CMOS, este hecho, junto con sus valores reducidos de área y consumo, lo hacen especialmente adecuado para la integración en un sistema de monitorización de DTM con un conjunto de monitores empotrados distribuidos a través del chip. Las crecientes incertidumbres de proceso asociadas a los últimos nodos tecnológicos comprometen las características de linealidad de nuestra primera propuesta de sensor. Con el objetivo de superar estos problemas, proponemos una nueva técnica para obtener la temperatura. La nueva técnica también está basada en las dependencias térmicas de las corrientes de fuga que se utilizan para descargar un nodo flotante. La novedad es que ahora la medida viene dada por el cociente de dos medidas diferentes, en una de las cuales se altera una característica del transistor de descarga |la tensión de puerta. Este cociente resulta ser muy robusto frente a variaciones de proceso y, además, la linealidad obtenida cumple ampliamente los requisitos impuestos por las políticas DTM |error 3_ de 1,17oC considerando variaciones del proceso y calibrando en dos puntos. La implementación de la parte sensora de esta nueva técnica implica varias consideraciones de diseño, tales como la generación de una referencia de tensión independiente de variaciones de proceso, que se analizan en profundidad en la tesis. Para la conversión tiempo-a-digital, se emplea la misma estructura de digitalización que en el primer sensor. Para la implementación física de la parte de digitalización, se ha construido una biblioteca de células estándar completamente nueva orientada a la reducción de área y consumo. El sensor resultante de la unión de todos los bloques se caracteriza por una energía por muestra ultra baja (48-640 pJ) y un área diminuta de 0,0016 mm2, esta cifra mejora todos los trabajos previos. Para probar esta afirmación, se realiza una comparación exhaustiva con más de 40 propuestas de sensores en la literatura científica. Subiendo el nivel de abstracción al sistema, la tercera contribución se centra en el modelado de un sistema de monitorización que consiste de un conjunto de sensores distribuidos por la superficie del chip. Todos los trabajos anteriores de la literatura tienen como objetivo maximizar la precisión del sistema con el mínimo número de monitores. Como novedad, en nuestra propuesta se introducen nuevos parámetros de calidad aparte del número de sensores, también se considera el consumo de energía, la frecuencia de muestreo, los costes de interconexión y la posibilidad de elegir diferentes tipos de monitores. El modelo se introduce en un algoritmo de recocido simulado que recibe la información térmica de un sistema, sus propiedades físicas, limitaciones de área, potencia e interconexión y una colección de tipos de monitor; el algoritmo proporciona el tipo seleccionado de monitor, el número de monitores, su posición y la velocidad de muestreo _optima. Para probar la validez del algoritmo, se presentan varios casos de estudio para el procesador Alpha 21364 considerando distintas restricciones. En comparación con otros trabajos previos en la literatura, el modelo que aquí se presenta es el más completo. Finalmente, la última contribución se dirige al nivel de red, partiendo de un conjunto de monitores de temperatura de posiciones conocidas, nos concentramos en resolver el problema de la conexión de los sensores de una forma eficiente en área y consumo. Nuestra primera propuesta en este campo es la introducción de un nuevo nivel en la jerarquía de interconexión, el nivel de trillado (o threshing en inglés), entre los monitores y los buses tradicionales de periféricos. En este nuevo nivel se aplica selectividad de datos para reducir la cantidad de información que se envía al controlador central. La idea detrás de este nuevo nivel es que en este tipo de redes la mayoría de los datos es inútil, porque desde el punto de vista del controlador sólo una pequeña cantidad de datos |normalmente sólo los valores extremos| es de interés. Para cubrir el nuevo nivel, proponemos una red de monitorización mono-conexión que se basa en un esquema de señalización en el dominio de tiempo. Este esquema reduce significativamente tanto la actividad de conmutación sobre la conexión como el consumo de energía de la red. Otra ventaja de este esquema es que los datos de los monitores llegan directamente ordenados al controlador. Si este tipo de señalización se aplica a sensores que realizan conversión tiempo-a-digital, se puede obtener compartición de recursos de digitalización tanto en tiempo como en espacio, lo que supone un importante ahorro de área y consumo. Finalmente, se presentan dos prototipos de sistemas de monitorización completos que de manera significativa superan la características de trabajos anteriores en términos de área y, especialmente, consumo de energía. Abstract Temperature is a first class design concern in modern integrated circuits. The important increase in power densities associated to recent technology evolutions has lead to the apparition of thermal gradients and hot spots during run time operation. Temperature impacts several circuit parameters such as speed, cooling budgets, reliability, power consumption, etc. In order to fight against these negative effects, dynamic thermal management (DTM) techniques adapt the behavior of the chip relying on the information of a monitoring system that provides run-time thermal information of the die surface. The field of on-chip temperature monitoring has drawn the attention of the scientific community in the recent years and is the object of study of this thesis. This thesis approaches the matter of on-chip temperature monitoring from different perspectives and levels, providing solutions to some of the most important issues. The physical and circuital levels are covered with the design and characterization of two novel temperature sensors specially tailored for DTM purposes. The first sensor is based upon a mechanism that obtains a pulse with a varying width based on the variations of the leakage currents on the temperature. In a nutshell, a circuit node is charged and subsequently left floating so that it discharges away through the subthreshold currents of a transistor; the time the node takes to discharge is the width of the pulse. Since the width of the pulse displays an exponential dependence on the temperature, the conversion into a digital word is realized by means of a logarithmic counter that performs both the timeto- digital conversion and the linearization of the output. The structure resulting from this combination of elements is implemented in a 0.35_m technology and is characterized by very reduced area, 10250 nm2, and power consumption, 1.05-65.5 nW at 5 samples/s, these figures outperformed all previous works by the time it was first published and still, by the time of the publication of this thesis, they outnumber all previous implementations in the same technology node. Concerning the accuracy, the sensor exhibits good linearity, even without calibration it displays a 3_ error of 1.97oC, appropriate to deal with DTM applications. As explained, the sensor is completely compatible with standard CMOS processes, this fact, along with its tiny area and power overhead, makes it specially suitable for the integration in a DTM monitoring system with a collection of on-chip monitors distributed across the chip. The exacerbated process fluctuations carried along with recent technology nodes jeop-ardize the linearity characteristics of the first sensor. In order to overcome these problems, a new temperature inferring technique is proposed. In this case, we also rely on the thermal dependencies of leakage currents that are used to discharge a floating node, but now, the result comes from the ratio of two different measures, in one of which we alter a characteristic of the discharging transistor |the gate voltage. This ratio proves to be very robust against process variations and displays a more than suficient linearity on the temperature |1.17oC 3_ error considering process variations and performing two-point calibration. The implementation of the sensing part based on this new technique implies several issues, such as the generation of process variations independent voltage reference, that are analyzed in depth in the thesis. In order to perform the time-to-digital conversion, we employ the same digitization structure the former sensor used. A completely new standard cell library targeting low area and power overhead is built from scratch to implement the digitization part. Putting all the pieces together, we achieve a complete sensor system that is characterized by ultra low energy per conversion of 48-640pJ and area of 0.0016mm2, this figure outperforms all previous works. To prove this statement, we perform a thorough comparison with over 40 works from the scientific literature. Moving up to the system level, the third contribution is centered on the modeling of a monitoring system consisting of set of thermal sensors distributed across the chip. All previous works from the literature target maximizing the accuracy of the system with the minimum number of monitors. In contrast, we introduce new metrics of quality apart form just the number of sensors; we consider the power consumption, the sampling frequency, the possibility to consider different types of monitors and the interconnection costs. The model is introduced in a simulated annealing algorithm that receives the thermal information of a system, its physical properties, area, power and interconnection constraints and a collection of monitor types; the algorithm yields the selected type of monitor, the number of monitors, their position and the optimum sampling rate. We test the algorithm with the Alpha 21364 processor under several constraint configurations to prove its validity. When compared to other previous works in the literature, the modeling presented here is the most complete. Finally, the last contribution targets the networking level, given an allocated set of temperature monitors, we focused on solving the problem of connecting them in an efficient way from the area and power perspectives. Our first proposal in this area is the introduction of a new interconnection hierarchy level, the threshing level, in between the monitors and the traditional peripheral buses that applies data selectivity to reduce the amount of information that is sent to the central controller. The idea behind this new level is that in this kind of networks most data are useless because from the controller viewpoint just a small amount of data |normally extreme values| is of interest. To cover the new interconnection level, we propose a single-wire monitoring network based on a time-domain signaling scheme that significantly reduces both the switching activity over the wire and the power consumption of the network. This scheme codes the information in the time domain and allows a straightforward obtention of an ordered list of values from the maximum to the minimum. If the scheme is applied to monitors that employ TDC, digitization resource sharing is achieved, producing an important saving in area and power consumption. Two prototypes of complete monitoring systems are presented, they significantly overcome previous works in terms of area and, specially, power consumption.

Progress in single junction microcrystalline silicon solar cells deposited by Hot-Wire CVD

Hot-Wire Chemical Vapor Deposition has led to microcrystalline silicon solar cell efficiencies similar to those obtained with Plasma Enhanced CVD. The light-induced degradation behavior of microcrystalline silicon solar cells critically depends on the properties of their active layer. In the regime close to the transition to amorphous growth (around 60% of amorphous volume fraction), cells incorporating an intrinsic layer with slightly higher crystalline fraction and [220] preferential orientation are stable after more than 7000 h of AM1.5 light soaking. On the contrary, solar cells whose intrinsic layer has a slightly lower crystalline fraction and random or [111] preferential orientation exhibit clear light-induced degradation effects. A revision of the efficiencies of Hot-Wire deposited microcrystalline silicon solar cells is presented and the potential efficiency of this technology is also evaluated.

Operator's, organizational and direct support maintenance manual : air conditioner, wall or base mounted, self-contained, multi-package, standard weight, air cooled, 6,000 BTU/hr cooling, 4,000 BTU/hr heating, class 1, 115 volt, single phase, 2-wire, 50/60 hertz, model CE-6A-60, Keco model F6000-7, NSN 4120-01-066-9677.

"21 November 1980."

Organizational and direct support maintenance repair parts and special tools list : air conditioner, wall or base mounted, self-contained, multi-package, standard weight, air cooled, 6,000 BTU/hr cooling, 4,500 BTU/hr heating, class 1, 115 volt, single phase, 2-wire, 50/60 Hertz, model CE-6A-60, Keco model F6000-7, NSN 4120-01-066-9677.

Includes index.