A side-sensitive synthetic chart combined with an X chart

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

The steady-state behavior of the synthetic and side-sensitive synthetic double sampling (X)over-bar charts

The steady-state average run length is used to measure the performance of the recently proposed synthetic double sampling (X) over bar chart (synthetic DS chart). The overall performance of the DS X chart in signaling process mean shifts of different magnitudes does not improve when it is integrated with the conforming run length chart, except when the integrated charts are designed to offer very high protection against false alarms, and the use of large samples is prohibitive. The synthetic chart signals when a second point falls beyond the control limits, no matter whether one of them falls above the centerline and the other falls below it; with the side-sensitive feature, the synthetic chart does not signal when they fall on opposite sides of the centerline. We also investigated the steady-state average run length of the side-sensitive synthetic DS X chart. With the side-sensitive feature, the overall performance of the synthetic DS X chart improves, but not enough to outperform the non-synthetic DS X chart. Copyright (C) 2014 John Wiley &Sons, Ltd.

Some Comments Regarding the Synthetic (X)over-bar Chart

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Temperature-Sensitive Src-Transformed Mdck Cells nn 3d Cultures as a Model of Malignant Transformation of Epithelial Cells

The equilibrium between cell proliferation, differentiation, and apoptosis is crucial for maintaining homeostasis in epithelial tissues. In order for the epithelium to function properly, individual cells must gain normal structural and functional polarity. The junctional proteins have an important role both in binding the cells together and in taking part in cell signaling. Cadherins form adherens junctions. Cadherins initiate the polarization process by first recognizing and binding the neighboring cells together, and then guiding the formation of tight junctions. Tight junctions form a barrier in dividing the plasma membranes to apical and basolateral membrane domains. In glandular tissues, single layered and polarized epithelium is folded into tubes or spheres, in which the basal side of the epithelial layer faces the outer basal membrane, and the apical side the lumen. In carcinogenesis, the differentiated architecture of an epithelial layer is disrupted. Filling of the luminal space is a hallmark of early epithelial tumors in tubular and glandular structures. In order for the transformed tumor cells to populate the lumen, enhanced proliferation as well as inhibition of apoptosis is required. Most advances in cancer biology have been achieved by using two-dimensional (2D) cell culture models, in which the cells are cultured on flat surfaces as monolayers. However, the 2D cultures are limited in their capacity to recapitulate the structural and functional features of tubular structures and to represent cell growth and differentiation in vivo. The development of three-dimensional (3D) cell culture methods enables the cells to grow and to be studied in a more natural environment. Despite the wide use of 2D cell culture models and the development of novel 3D culture methods, it is not clear how the change of the dimensionality of culture conditions alters the polarization and transformation process and the molecular mechanisms behind them. Src is a well-known oncogene. It is found in focal and adherens junctions of cultured cells. Active src disrupts cell-cell junctions and interferes with cell-matrix binding. It promotes cell motility and survival. Src transformation in 2D disrupts adherens junctions and the fibroblastic phenotype of the cells. In 3D, the adherens junctions are weakened, and in glandular structures, the lumen is filled with nonpolarized vital cells. Madin-Darby canine kidney (MDCK) cells are an epithelial cell type commonly used as a model for cell polarization. Its-src-transformed variants are useful model systems for analyzing the changes in cell morphology, and they play a role in src-induced malignant transformation. This study investigates src-transformed cells in 3D cell cultures as a model for malignant transformation. The following questions were posed. Firstly: What is the role of the composition and stiffness of the extracellular matrix (ECM) on the polarization and transformation of ts v-src MDCK cells in 3D cell cultures? Secondly: How do the culture conditions affect gene expression? What is the effect of v-src transformation in 2D and in 3D cell models? How does the shift from 2D to 3D affect cell polarity and gene expression? Thirdly: What is the role of survivin and its regulator phosphatase and tensin homolog protein (PTEN) in cell polarization and transformation, and in determining cell fate? How does their expression correlate with impaired mitochondrial function in transformed cells? In order to answer the above questions, novel methods of culturing and monitoring cells had to be created: novel 3D methods of culturing epithelial cells were engineered, enabling real time monitoring of a polarization and transformation process, and functional testing of 3D cell cultures. Novel 3D cell culture models and imaging techniques were created for the study. Attention was focused especially on confocal microscopy and live-cell imaging. Src-transformation disturbed the polarization of the epithelium by disrupting cell adhesion, and sensitized the cells to their environment. With active src, the morphology of the cell cluster depended on the composition and stiffness of the matrix. Gene expression studies revealed a broader impact of src transformation than mere continuous activity of src-kinase. In 2D cultures, src transformation altered the expression of immunological, actin cytoskeleton and extracellular matrix (ECM). In 3D, the genes regulating cell division, inhibition of apoptosis, cell metabolism, mitochondrial function, actin cytoskeleton and mechano-sensing proteins were altered. Surprisingly, changing the culture conditions from 2D to 3D affected also gene expression considerably. The microarray hit survivin, an inhibitor of apoptosis, played a crucial role in the survival and proliferation of src-transformed cells.

Survey report of NOAA Ship McArthur II cruises AR-04-04, AR-05-05 and AR-06-03: Habitat classification of side scan sonar imagery in support of deep-sea coral/sponge explorations at the Olympic Coast National Marine Sanctuary

Habitat mapping and characterization has been defined as a high-priority management issue for the Olympic Coast National Marine Sanctuary (OCNMS), especially for poorly known deep-sea habitats that may be sensitive to anthropogenic disturbance. As a result, a team of scientists from OCNMS, National Centers for Coastal Ocean Science (NCCOS), and other partnering institutions initiated a series of surveys to assess the distribution of deep-sea coral/sponge assemblages within the sanctuary and to look for evidence of potential anthropogenic impacts in these critical habitats. Initial results indicated that remotely delineating areas of hard bottom substrate through acoustic sensing could be a useful tool to increase the efficiency and success of subsequent ROV-based surveys of the associated deep-sea fauna. Accordingly, side scan sonar surveys were conducted in May 2004, June 2005, and April 2006 aboard the NOAA Ship McArthur II to: (1) obtain additional imagery of the seafloor for broader habitat-mapping coverage of sanctuary waters, and (2) help delineate suitable deep-sea coral/sponge habitat, in areas of both high and low commercial-fishing activities, to serve as sites for surveying-in more detail using an ROV on subsequent cruises. Several regions of the sea floor throughout the OCNMS were surveyed and mosaicked at 1-meter pixel resolution. Imagery from the side scan sonar mapping efforts was integrated with other complementary data from a towed camera sled, ROVs, sedimentary samples, and bathymetry records to describe geological and biological (where possible) aspects of habitat. Using a hierarchical deep-water marine benthic classification scheme (Greene et al. 1999), we created a preliminary map of various habitat polygon features for use in a geographical information system (GIS). This report provides a description of the mapping and groundtruthing efforts as well as results of the image classification procedure for each of the areas surveyed. (PDF contains 60 pages.)

Pre-Processing Power Traces with a Phase-Sensitive Detector

As cryptographic implementations are increasingly subsumed as functional blocks within larger systems on chip, it becomes more difficult to identify the power consumption signatures of cryptographic operations amongst other unrelated processing activities. In addition, at higher clock frequencies, the current decay between successive processing rounds is only partial, making it more difficult to apply existing pattern matching techniques in side-channel analysis. We show however, through the use of a phase-sensitive detector, that power traces can be pre-processed to generate a filtered output which exhibits an enhanced round pattern, enabling the identification of locations on a device where encryption operations are occurring and also assisting with the re-alignment of power traces for side-channel attacks.

The dark side of CRM: advantaged and disadvantaged customers

Purpose – CRM treats various profiles of customers or individual customers differently, purposively favoring certain customers while deliberately disadvantaging others. This research aims to provide insights into how advantaged (favored) and (non-favored) disadvantaged customers perceive fairness in retailers’ marketing tactics. Design/methodology/approach – A multiple study approach has been adopted, influenced by a three-stage process, which involved exploratory interviews, pilot tests, and the main survey. Findings – The results have provided marketers with a perspective on maintaining and enhancing relationships. Service and marketing communications concern the advantaged customers most, while pricing is the most important aspect for the disadvantaged customers. Practical implications – In terms of handling customers, there are important implications from recognizing how those who are favored and those who are not so advantaged perceive their treatment. Failure to appreciate the pitfalls for visibly treating certain customers more favorably and others demonstrably less so, will have stark consequences for retail management and consumer marketing. Originality/value – Contributions are made to the literatures on CRM and on unfairness, particularly in terms of how to address the inevitable inequities inherent in retailers’ CRM offerings. Identification of the advantaged and disadvantaged customers and their respective views allows marketers to develop more appropriate approaches for handling customers who are sensitive to perceived unfairness.

DC and AC side harmonics in CCC converters

The capacitor-commutated converter (CCC) has frequently been used in the conception of HVDC systems connected to busbars with low short circuit level. This alternative arrangement, in substitution to the conventional ones, guarantees less sensitive operational conditions to problems related with the commutation failure in the inverters besides supplying part of the reactive energy to be compensated. Studies related with its performance in steady and transient states have been presented in several works, however its behavior as harmonic source is still little explored. This work presents preliminary studies focusing the generation of characteristic harmonics by this type of converter. Subjects related with the amplification of the harmonic magnitudes are investigated and compared considering similar arrangements of conventional static converters (LCC) and CCC schemes. It is also analyzed the harmonic generation on the dc side of the installation and its influence on the ac side harmonics. The results are obtained from simulations in the time domain in PSpice environment and they clearly illustrate the operational differences between the L CC and the CCC schemes with regard to characteristic harmonic generation.

Gait analysis in clinically healthy sheep from three different age groups using a pressure-sensitive walkway

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Competition Between Novelty and Cocaine Conditioned Reward Is Sensitive to Drug Dose and Retention Interval

The conditioned rewarding effects of novelty compete with those of cocaine for control over choice behavior using a place conditioning task. The purpose of the present study was to use multiple doses of cocaine to determine the extent of this competition and to determine whether novelty’s impact on cocaine reward was maintained over an abstinence period. In Experiment 1, rats were conditioned with cocaine (7.5, 20, or 30 mg/kg ip) to prefer one side of an unbiased place conditioning apparatus relative to the other. In a subsequent phase, all rats received alternating daily confinements to the previously cocaine paired and unpaired sides of the apparatus. During this phase, half the rats had access to a novel object on their initially unpaired side; the remaining rats did not receive objects. The ability of novelty to compete with cocaine in a drug free and cocaine challenge test was sensitive to cocaine dose. In Experiment 2, a place preference was established with 10 mg/kg cocaine and testing occurred after 1, 14, or 28 day retention intervals. Findings indicate that choice behaviors mediated by cocaine conditioning are reduced with the passing of time. Taken together, competition between cocaine and novelty conditioned rewards are sensitive to drug dose and retention interval.

A modified calculation of ankle-brachial pressure index is far more sensitive in the detection of peripheral arterial disease

BACKGROUND: Ankle-brachial pressure index (ABI) is a simple, inexpensive, and useful tool in the detection of peripheral arterial occlusive disease (PAD). The current guidelines published by the American Heart Association define ABI as the quotient of the higher of the systolic blood pressures (SBPs) of the two ankle arteries of that limb (either the anterior tibial artery or the posterior tibial artery) and the higher of the two brachial SBPs of the upper limbs. We hypothesized that considering the lower of the two ankle arterial SBPs of a side as the numerator and the higher of the brachial SBPs as the denominator would increase its diagnostic yield. METHODS: The former method of eliciting ABI was termed as high ankle pressure (HAP) and the latter low ankle pressure (LAP). ABI was assessed in 216 subjects and calculated according to the HAP and the LAP method. ABI findings were confirmed by arterial duplex ultrasonography. A significant arterial stenosis was assumed if ABI was <0.9. RESULTS: LAP had a sensitivity of 0.89 and a specificity of 0.93. The HAP method had a sensitivity of 0.68 and a specificity of 0.99. McNemar's test to compare the results of both methods demonstrated a two-tailed P < .0001, indicating a highly significant difference between both measurement methods. CONCLUSIONS: LAP is the superior method of calculating ABI to identify PAD. This result is of great interest for epidemiologic studies applying ABI measurements to detect PAD and assessing patients' cardiovascular risk.

Epothilone analogues with benzimidazole and quinoline side chains: chemical synthesis, antiproliferative activity, and interactions with tubulin

A series of epothilone B and D analogues bearing isomeric quinoline or functionalized benzimidazole side chains has been prepared by chemical synthesis in a highly convergent manner. All analogues have been found to interact with the tubulin/microtubule system and to inhibit human cancer cell proliferation in vitro, albeit with different potencies (IC(50) values between 1 and 150 nM). The affinity of quinoline-based epothilone B and D analogues for stabilized microtubules clearly depends on the position of the N-atom in the quinoline system, while the induction of tubulin polymerization in vitro appears to be less sensitive to N-positioning. The potent inhibition of human cancer cell growth by epothilone analogues bearing functionalized benzimidazole side chains suggests that these systems might be conjugated with tumor-targeting moieties to form tumor-targeted prodrugs.

Different dark conformations function in color-sensitive photosignaling by the sensory rhodopsin I-HtrI complex.

The haloarchaeal phototaxis receptor sensory rhodopsin I (SRI) in complex with its transducer HtrI delivers an attractant signal from excitation with an orange photon and a repellent signal from a second near-UV photon excitation. Using a proteoliposome system with purified SRI in complex with its transducer HtrI, we identified by site-directed fluorescence labeling a site (Ser(155)) on SRI that is conformationally active in signal relay to HtrI. Using site-directed spin labeling of Ser(155)Cys with a nitroxide side chain, we detected a change in conformation following one-photon excitation such that the spin probe exhibits a splitting of the outer hyperfine extrema (2A'(zz)) significantly smaller than that of the electron paramagnetic resonance spectrum in the dark state. The dark conformations of five mutant complexes that do not discriminate between orange and near-UV excitation show shifts to lower or higher 2A'(zz) values correlated with the alterations in their motility behavior to one- and two-photon stimuli. These data are interpreted in terms of a model in which the dark complex is populated by two conformers in the wild type, one that inhibits the CheA kinase (A) and the other that activates it (R), shifted in the dark by mutations and shifted in the wild-type SRI-HtrI complex in opposite directions by one-photon and two-photon reactions.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.