IRTOPALATERÄN KEHITTÄMINEN SÄRMÄ- JA PROFILOINTIHAKETUKSEEN

Diplomityön tarkoituksena on kehittää irtopalaterä sahahakkeen valmistukseen. Tutkimuksessa perehdytään lastun irtoamisen perusteisiin ja lastun kulkeutumiseen ulos terältä. Tutkimuksessa keskeisenä osana ovat laboratoriokokeet joissa suurnopeuskameralla kuvaamalla selvitetään lastun kulkeutuminen. Saatujen tulosten perusteella muodostetaan terän toimivuuden kannalta keskeiset suunnitteluperusteet. Tutkimuksen kirjallisessa osuudessa selvitetään lastun muodostuminen ja siihen vaikuttavat tekijät.

Eräällä pelkkahakkurilla tuotetun selluhakkeen laatujakauman hallinta

Tämän diplomityön tarkoituksena on selvittää eräällä pelkkahakkurilla tuotetun selluhakkeen laadun vaihtelua ja laadun hallinnan mahdollisuuksia. Tutkittu laite on Veisto Oy:n suunnittelema ja valmistama HewSaw R200 - pelkkahakkuri. Tutkimuksessa selvitetään sahauksen yhteydessä pelkkahakkurilla tuotettavaan selluhakkeeseen vaikuttavien parametrien: hakkurin pyörimisnopeuden, tukin syöttönopeuden, hakkurin terien vaihtovälin, selluhakkeen palakoon, tukkiluokan, puun lämpötilan ja puulajin välisiä korrelaatioita ja edellä mainittujen tekijöiden vaikutusta tuotettavan hakkeen palakokojakaumaan. Tämä palakokojakauma määrää selluhakkeen laadunmäärityksessä käytettävän, niin sanotun hintakertoimen. Kyseinen hintakerroin määritellään SCAN – CM 40 – standardin mukaisella seulonnalla. Tämä standardi on käytössä laadunmäärityksen perusteena kaikilla pohjoismaisilla sellutehtailla.Tutkimuksen kirjallisessa osuudessa esitellään sahateollisuuden merkittävimmät sahausmenetelmät ja sivuotteiden tuotanto . Seuraavassa osassa käsitellään erikseen selluhaketta sahateollisuuden sivutuotteena ja sen taloudellista merkitystä sahateollisuudessa. Jatkossa keskitytään selluhakkeen tuottamiseen pelkkahakkurilla ja puun työstämiseen liittyviin periaatteisiin.Tutkimuksen kokeellisessa osuudessa tutkittaan, eri sahalaitoksilta otettujen hakenäytteiden perusteella, tärkeimmiksi havaittujen tuotantoparametrien vaikutusta selluhakkeen laatuun ja saantoon. Näytteitä otettiin tutkimuksen kokeellisessa osuudessa yhteensä noin 250 kappaletta. Tutkimuksen tuloksia käsittelevässä osuudessa on annettu malli tutkitulla HewSaw R200 - pelkkahakkurilla tuotetun selluhakkeen laadun ja määrän arvioimiseen.

Surface-acoustic-wave counterflow micropumps for on-chip liquid motion control in two-dimensional microchannel arrays

Fully controlled liquid injection and flow in hydrophobic polydimethylsiloxane (PDMS) two-dimensional microchannel arrays based on on-chip integrated, low-voltage-driven micropumps are demonstrated. Our architecture exploits the surface-acoustic-wave (SAW) induced counterflow mechanism and the effect of nebulization anisotropies at crossing areas owing to lateral propagating SAWs. We show that by selectively exciting single or multiple SAWs, fluids can be drawn from their reservoirs and moved towards selected positions of a microchannel grid. Splitting of the main liquid flow is also demonstrated by exploiting multiple SAW beams. As a demonstrator, we show simultaneous filling of two orthogonal microchannels. The present results show that SAW micropumps are good candidates for truly integrated on-chip fluidic networks allowing liquid control in arbitrarily shaped two-dimensional microchannel arrays.

Comparison between DC(+) and Square Wave AC SAW Current Outputs to Weld AISI 304 for Low-Temperature Applications

Welded equipment for cryogenic applications is utilized in chemical, petrochemical, and metallurgical industries. One material suitable for cryogenic application is austenitic stainless steel, which usually doesn`t present ductile/brittle transition temperature, except in the weld metal, where the presence of ferrite and micro inclusions can promote a brittle failure, either by ferrite cleavage or dimple nucleation and growth, respectively. A 25-mm- (1-in.-) thick AISI 304 stainless steel base metal was welded with the SAW process using a 308L solid wire and two kinds of fluxes and constant voltage power sources with two types of electrical outputs: direct current electrode positive and balanced square wave alternating current. The welded joints were analyzed by chemical composition, microstructure characterization, room temperature mechanical properties, and CVN impact test at -100 degrees C (-73 degrees F). Results showed that an increase of chromium and nickel content was observed in all weld beads compared to base metal. The chromium and nickel equivalents ratio for the weld beads were always higher for welding with square wave AC for the two types of fluxes than for direct current. The modification in the Cr(eq)/Ni(eq) ratio changes the delta ferrite morphology and, consequently, modifies the weld bead toughness at lower temperatures. The oxygen content can also affect the toughness in the weld bead. The highest absorbed energy in a CVN impact test was obtained for the welding condition with square wave AC electrical output and neutral flux, followed by DC(+) electrical output and neutral flux, and square wave AC electrical output and alloyed flux.

Negative ion `chip-based` nanospray tandem mass spectrometry for the analysis of flavonoids in glandular trichomes of Lychnophora ericoides Mart. (Asteraceae)

This paper reports a method for the analysis of secondary metabolites stored in glandular trichomes, employing negative ion `chip-based` nanospray tandem mass spectrometry. The analyses of glandular trichomes from Lychnophora ericoides, a plant endemic to the Brazilian `cerrado` and used in traditional medicine as an anti-inflammatory and analgesic agent, led to the identification of five flavonoids (chrysin, pinocembrin, pinostrobin, pinobanksin and 3-O-acetylpinobanksin) by direct infusion of the extracts of glandular trichomes into the nanospray ionisation source. All the flavonoids have no oxidation at ring B, which resulted in a modification of the fragmentation pathways compared with that of the oxidised 3,4-dihydroflavonoids already described in the literature. The absence of the anti-inflammatory and antioxidant di-C-glucosylflavone vicenin-2, or any other flavonoid glycosides, in the glandular trichomes was also demonstrated. The use of the,`chip-based` nanospray QqTOF apparatus is a new fast and useful tool for the identification of secondary metabolites stored in the glandular trichomes, which can be useful for chemotaxonomic studies based on metabolites from glandular trichomes. Copyright (C) 2008 John Wiley & Sons, Ltd.

Foil based atom chip for Bose-Einstein condensates

We describe a novel method of fabricating atom chips that are well suited to the production and manipulation of atomic Bose–Einstein condensates. Our chip was created using a silver foil and simple micro-cutting techniques without the need for photolithography. It can sustain larger currents than conventional chips, and is compatible with the patterning of complex trapping potentials. A near pure Bose–Einstein condensate of 4 × 104 87Rb atoms has been created in a magnetic microtrap formed by currents through wires on the chip. We have observed the fragmentation of atom clouds in close proximity to the silver conductors. The fragmentation has different characteristic features to those seen with copper conductors.

Towards network-on-chip agreement protocols

Demands for functionality enhancements, cost reductions and power savings clearly suggest the introduction of multiand many-core platforms in real-time embedded systems. However, when compared to uni-core platforms, the manycores experience additional problems, namely the lack of scalable coherence mechanisms and the necessity to perform migrations. These problems have to be addressed before such systems can be considered for integration into the realtime embedded domain. We have devised several agreement protocols which solve some of the aforementioned issues. The protocols allow the applications to plan and organise their future executions both temporally and spatially (i.e. when and where the next job will be executed). Decisions can be driven by several factors, e.g. load balancing, energy savings and thermal issues. All presented protocols are analytically described, with the particular emphasis on their respective real-time behaviours and worst-case performance. The underlying assumptions are based on the multi-kernel model and the message-passing paradigm, which constitutes the communication between the interacting instances.

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing

Hyperspectral instruments have been incorporated in satellite missions, providing large amounts of data of high spectral resolution of the Earth surface. This data can be used in remote sensing applications that often require a real-time or near-real-time response. To avoid delays between hyperspectral image acquisition and its interpretation, the last usually done on a ground station, onboard systems have emerged to process data, reducing the volume of information to transfer from the satellite to the ground station. For this purpose, compact reconfigurable hardware modules, such as field-programmable gate arrays (FPGAs), are widely used. This paper proposes an FPGA-based architecture for hyperspectral unmixing. This method based on the vertex component analysis (VCA) and it works without a dimensionality reduction preprocessing step. The architecture has been designed for a low-cost Xilinx Zynq board with a Zynq-7020 system-on-chip FPGA-based on the Artix-7 FPGA programmable logic and tested using real hyperspectral data. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low-cost embedded systems, opening perspectives for onboard hyperspectral image processing.

Partitioning the Network-on-Chip to Enable Virtualization on Many-Core Processors

6th International Real-Time Scheduling Open Problems Seminar (RTSOPS 2015), Lund, Sweden.

Desenvolvimento de um biossensor de ADN integrado num chip de microfluídica

Dissertação para obtenção do Grau de Mestre em Engenharia Biomédica

PDMS encasing system for integrated lab-on-chip Ag/AgCl reference electrodes

Poly(dimethylsiloxane) (PDMS) is an organosilicon polymer widely used in the fabrication of microfluidic systems to integrate biochips. In this study, we propose the use of an adapted PDMS mould for the creation of a miniaturized, reusable, reference electrode for in-chip electrochemical measurements. Through its integrated microfluidic system it is possible to replenish internal buffer solutions, unclog critical junctions and treat the electrode’s surface, assuring a long term reuse of the same device. Planar Ag/AgCl reference electrodes were microfabricated over a passivated p-type Silicon Wafer. The PDMS mould, containing an integrated microfluidic system, was fabricated based on patterned SU-8 mould, which includes a lateral horizontal inlet access point. Surface oxidation was used for irreversible permanent bondage between flat surfaces. The final result was planar Ag/AgCl reference electrode with integrated microfluidic that allows for electrochemical analysis in biochips

Diseño de celdas analógicas embebidas en sistemas en un chip (SOC)

La metodología actual de diseño de celdas analógicas embebidas se basa en una tecnología CMOS fija, no teniendo dichos módulos características de reutilización y de migración hacia otras tecnologías. Para avanzar a un mayor nivel de productividad en el diseño se necesita un cambio de paradigma. Este cambio en la metodología necesita reducir tiempo y esfuerzo en el desarrollo, incrementar la predictibilidad y reducir el riesgo involucrado en el diseño y la fabricación de complejos sistemas en un chip (SOC). Las celdas digitales embebidas se han aplicado al diseño VLSI digital debido a que la síntesis a través de lenguajes de descripción de hardware (HDL) permite mapear complejos algoritmos en una descripción sintáctica digital, la cual puede luego ser automáticamente colocada e interconectada (place&route). Sin embargo, dada la falta de automatización del diseño electrónico en el dominio analógico, como así también por factores como el ruido, el corrimiento y falta de apareamiento, el uso de los circuitos analógicos ha sido muy bajo en la medida de lo posible, por lo que las celdas analógicas embebidas son ahora un cuello de botella en el diseño de SOC. Por lo expuesto, en el proyecto que se propone se planea diseñar celdas analógicas embebidas con características de: bajo consumo, reutilización, bajo costo y alta performance para satisfacer el notable crecimiento del mercado de los sistemas portables alimentados por batería y el de sistemas de identificación remotamente energizados (RFID). Conjuntamente con el Área de Comunicaciones, se propone un generador de tensión de alimentación a partir de una señal de RF.