The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

A CMOS micro power switched-capacitor DC-DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V-OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm(2) in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm(2), is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m(2). After starting-up, the system requires an irradiance of only 0.18 W/m(2) (18 mu W/cm(2)) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 mu W. These values are, to the best of the authors' knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 mu W, which is comparable with reported values from circuits operating at similar power levels.

CMOS indoor light energy harvesting system for wireless sensing applications

Dissertação para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores

Amorphous silicon e 3D sensors applied to object detection

Nowadays, existing 3D scanning cameras and microscopes in the market use digital or discrete sensors, such as CCDs or CMOS for object detection applications. However, these combined systems are not fast enough for some application scenarios since they require large data processing resources and can be cumbersome. Thereby, there is a clear interest in exploring the possibilities and performances of analogue sensors such as arrays of position sensitive detectors with the final goal of integrating them in 3D scanning cameras or microscopes for object detection purposes. The work performed in this thesis deals with the implementation of prototype systems in order to explore the application of object detection using amorphous silicon position sensors of 32 and 128 lines which were produced in the clean room at CENIMAT-CEMOP. During the first phase of this work, the fabrication and the study of the static and dynamic specifications of the sensors as well as their conditioning in relation to the existing scientific and technological knowledge became a starting point. Subsequently, relevant data acquisition and suitable signal processing electronics were assembled. Various prototypes were developed for the 32 and 128 array PSD sensors. Appropriate optical solutions were integrated to work together with the constructed prototypes, allowing the required experiments to be carried out and allowing the achievement of the results presented in this thesis. All control, data acquisition and 3D rendering platform software was implemented for the existing systems. All these components were combined together to form several integrated systems for the 32 and 128 line PSD 3D sensors. The performance of the 32 PSD array sensor and system was evaluated for machine vision applications such as for example 3D object rendering as well as for microscopy applications such as for example micro object movement detection. Trials were also performed involving the 128 array PSD sensor systems. Sensor channel non-linearities of approximately 4 to 7% were obtained. Overall results obtained show the possibility of using a linear array of 32/128 1D line sensors based on the amorphous silicon technology to render 3D profiles of objects. The system and setup presented allows 3D rendering at high speeds and at high frame rates. The minimum detail or gap that can be detected by the sensor system is approximately 350 μm when using this current setup. It is also possible to render an object in 3D within a scanning angle range of 15º to 85º and identify its real height as a function of the scanning angle and the image displacement distance on the sensor. Simple and not so simple objects, such as a rubber and a plastic fork, can be rendered in 3D properly and accurately also at high resolution, using this sensor and system platform. The nip structure sensor system can detect primary and even derived colors of objects by a proper adjustment of the integration time of the system and by combining white, red, green and blue (RGB) light sources. A mean colorimetric error of 25.7 was obtained. It is also possible to detect the movement of micrometer objects using the 32 PSD sensor system. This kind of setup offers the possibility to detect if a micro object is moving, what are its dimensions and what is its position in two dimensions, even at high speeds. Results show a non-linearity of about 3% and a spatial resolution of < 2µm.

Design of a CMOS amplifier for breast cancer detection

A transimpedance amplifier (TIA) is used, in radiation detectors like the positron emission tomography(PET), to transform the current pulse produced by a photo-sensitive device into an output voltage pulse with a desired amplitude and shape. The TIA must have the lowest noise possible to maximize the output. To achieve a low noise, a circuit topology is proposed where an auxiliary path is added to the feedback TIA input, In this auxiliary path a differential transconductance block is used to transform the node voltage in to a current, this current is then converted to a voltage pulse by a second feedback TIA complementary to the first one, with the same amplitude but 180º out of phase with the first feedback TIA. With this circuit the input signal of the TIA appears differential at the output, this is used to try an reduced the circuit noise. The circuit is tested with two different devices, the Avalanche photodiodes (APD) and the Silicon photomultiplier (SIPMs). From the simulations we find that when using s SIPM with Rx=20kΩ and Cx=50fF the signal to noise ratio is increased from 59 when using only one feedback TIA to 68.3 when we use an auxiliary path in conjunction with the feedback TIA. This values where achieved with a total power consumption of 4.82mv. While the signal to noise ratio in the case of the SIPM is increased with some penalty in power consumption.

Electroluminiscence and optical amplification in silicon nanostructures: towards the integration of electronics and photonics

This line of research of my group intends to establish a Silicon technological platform in the field of photonics allowing the development of a wide set of applications. Particularly, what is still lacking in Silicon Photonics is an efficient and integrable light source such an LED or laser. Nanocrystals in silicon oxide or nitride matrices have been recently demonstrated as competitive materials for both active components (electrically and optically driven light emitters and optical amplifiers) and passive ones (waveguides and modulators). The final goal is the achievement of a complete integration of electronic and optical functions in the same CMOS chip. The first part of this paper will introduce the structural and optical properties of LEDs fabricated from silicon nanostructures. The second will treat the interaction of such nanocrystals with rare-earth elements (Er), which lead to an efficient hybrid system emitting in the third window of optical fibers. I will present the fabrication and assessment of optical waveguide amplifiers at 1.54 ¿m for which we have been able to demonstrate recently optical gain in waveguides made from sputtered silicon suboxide materials.

CMOS-based active pixel for low-light-level detection: Analysis and measurements

An analysis of the active pixel sensor (APS), considering the doping profiles of the photodiode in an APS fabricated in a 0.18 μm standard CMOS technology, is presented. A simple and accurate model for the junction capacitance of the photodiode is proposed. An analytic expression for the output voltage of the APS obtained with this capacitance model is in good agreement with measurements and is more accurate than the models used previously. A different mode of operation for the APS based on the dc level of the output is suggested. This new mode has better low-light-level sensitivity than the conventional APS operating mode, and it has a slower temporal response to the change of the incident light power. At 1μW/cm2 and lower levels of light, the measured signal-to-noise ratio (SNR) of this new mode is more than 10 dB higher than the SNR of previously reported APS circuits. Also, with an output SNR of about 10 dB, the proposed dc level is capable of detecting light powers as low as 20 nW/cm2, which is about 30 times lower than the light power detected in recent reports by other groups. © 2007 IEEE.

Photodetection with gate-controlled lateral BJTs from standard CMOS technology

The silicon-based gate-controlled lateral bipolar junction transistor (BJT) is a controllable four-terminal photodetector with very high responsivity at low-light intensities. It is a hybrid device composed of a MOSFET, a lateral BJT, and a vertical BJT. Using sufficient gate bias to operate the MOS transistor in inversion mode, the photodetector allows for increasing the photocurrent gain by 106 at low light intensities when the base-emitter voltage is smaller than 0.4 V, and BJT is off. Two operation modes, with constant voltage bias between gate and emitter/source terminals and between gate and base/body terminals, allow for tuning the photoresponse from sublinear to slightly above linear, satisfying the application requirements for wide dynamic range, high-contrast, or linear imaging. MOSFETs from a standard 0.18-μm triple-well complementary-metal oxide semiconductor technology with a width to length ratio of 8 μm /2 μm and a total area of ∼ 500μm2 are used. When using this area, the responsivities are 16-20 kA/W. © 2001-2012 IEEE.

A low-power silicon-on-insulator PWM discriminator for biomedical applications

A CMOS/SOI circuit to decode PWM signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a double-integration concept and does not require dc filtering. Nonoverlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 mu m single-metal SOI fabrication process and has an effective area of 2mm(2) Typically, the measured resolution of encoding parameter a was better than 10% at 6MHz and V-DD=3.3V. Stand-by consumption is around 340 mu W. Pulses with frequencies up to 15MHz and alpha = 10% can be discriminated for V-DD spanning from 2.3V to 3.3V. Such an excellent immunity to V-DD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

A Low Power CMOS Voltage Regulator for a Wireless Blood Pressure Biosensor

This paper describes a CMOS implementation of a linear voltage regulator (LVR) used to power up implanted physiological signal systems, as it is the case of a wireless blood pressure biosensor. The topology is based on a classical structure of a linear low-dropout regulator. The circuit is powered up from an RF link, thus characterizing a passive radio frequency identification (RFID) tag. The LVR was designed to meet important features such as low power consumption and small silicon area, without the need for any external discrete components. The low power operation represents an essential condition to avoid a high-energy RF link, thus minimizing the transmitted power and therefore minimizing the thermal effects on the patient's tissues. The project was implemented in a 0.35-mu m CMOS process, and the prototypes were tested to validate the overall performance. The LVR output is regulated at 1 V and supplies a maximum load current of 0.5 mA at 37 degrees C. The load regulation is 13 mV/mA, and the line regulation is 39 mV/V. The LVR total power consumption is 1.2 mW.

CMoS lab-on-a-chip devices for individual cell biology

The development of microlectronic lab-on-a-chip devices (LOACs) can now be pursued thanks to the continous advances in silicon technology. LOACs are miniaturized devices whose aim is to perform in a more efficient way specific chemical or biological analysis protocols which are usually carried out with traditional laboratory equipment. In this application area, CMOS technology has the potential to integrate LOAC functionalities for cell biology applications in single chips, e.g. sensors, actuators, signal conditioning and processing circuits. In this work, after a review of the state of the art, the development of a CMOS prototype chip for individual cell manipulation and detection based on dielectrophoresis will be presented. Issues related to the embedded optical and capacitive detection of cells will be discussed together with the main experimental results obtained in manipulation and detection of living cells and microparticles.

Silicon Photonics Integrated Circuits for Flexible Optical Systems

This dissertation deals with the design and the characterization of novel reconfigurable silicon-on-insulator (SOI) devices to filter and route optical signals on-chip. Design is carried out through circuit simulations based on basic circuit elements (Building Blocks, BBs) in order to prove the feasibility of an approach allowing to move the design of Photonic Integrated Circuits (PICs) toward the system level. CMOS compatibility and large integration scale make SOI one of the most promising material to realize PICs. The concepts of generic foundry and BB based circuit simulations for the design are emerging as a solution to reduce the costs and increase the circuit complexity. To validate the BB based approach, the development of some of the most important BBs is performed first. A novel tunable coupler is also presented and it is demonstrated to be a valuable alternative to the known solutions. Two novel multi-element PICs are then analysed: a narrow linewidth single mode resonator and a passband filter with widely tunable bandwidth. Extensive circuit simulations are carried out to determine their performance, taking into account fabrication tolerances. The first PIC is based on two Grating Assisted Couplers in a ring resonator (RR) configuration. It is shown that a trade-off between performance, resonance bandwidth and device footprint has to be performed. The device could be employed to realize reconfigurable add-drop de/multiplexers. Sensitivity with respect to fabrication tolerances and spurious effects is however observed. The second PIC is based on an unbalanced Mach-Zehnder interferometer loaded with two RRs. Overall good performance and robustness to fabrication tolerances and nonlinear effects have confirmed its applicability for the realization of flexible optical systems. Simulated and measured devices behaviour is shown to be in agreement thus demonstrating the viability of a BB based approach to the design of complex PICs.

Silicon photonic device for wavelength sensing and monitoring

Over the last decade advances and innovations from Silicon Photonics technology were observed in the telecommunications and computing industries. This technology which employs Silicon as an optical medium, relies on current CMOS micro-electronics fabrication processes to enable medium scale integration of many nano-photonic devices to produce photonic integrated circuitry. ^ However, other fields of research such as optical sensor processing can benefit from silicon photonics technology, specially in sensors where the physical measurement is wavelength encoded. ^ In this research work, we present a design and application of a thermally tuned silicon photonic device as an optical sensor interrogator. ^ The main device is a micro-ring resonator filter of 10 μm of diameter. A photonic design toolkit was developed based on open source software from the research community. With those tools it was possible to estimate the resonance and spectral characteristics of the filter. From the obtained design parameters, a 7.8 × 3.8 mm optical chip was fabricated using standard micro-photonics techniques. In order to tune a ring resonance, Nichrome micro-heaters were fabricated on top of the device. Some fabricated devices were systematically characterized and their tuning response were determined. From measurements, a ring resonator with a free-spectral-range of 18.4 nm and with a bandwidth of 0.14 nm was obtained. Using just 5 mA it was possible to tune the device resonance up to 3 nm. ^ In order to apply our device as a sensor interrogator in this research, a model of wavelength estimation using time interval between peaks measurement technique was developed and simulations were carried out to assess its performance. To test the technique, an experiment using a Fiber Bragg grating optical sensor was set, and estimations of the wavelength shift of this sensor due to axial strains yield an error within 22 pm compared to measurements from spectrum analyzer. ^ Results from this study implies that signals from FBG sensors can be processed with good accuracy using a micro-ring device with the advantage of ts compact size, scalability and versatility. Additionally, the system also has additional applications such as processing optical wavelength shifts from integrated photonic sensors and to be able to track resonances from laser sources.^

Organic functionalisation, doping and characterisation of semiconductor surfaces for future CMOS device applications

Organic Functionalisation, Doping and Characterisation of Semiconductor Surfaces for Future CMOS Device Applications Semiconductor materials have long been the driving force for the advancement of technology since their inception in the mid-20th century. Traditionally, micro-electronic devices based upon these materials have scaled down in size and doubled in transistor density in accordance with the well-known Moore’s law, enabling consumer products with outstanding computational power at lower costs and with smaller footprints. According to the International Technology Roadmap for Semiconductors (ITRS), the scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) is proceeding at a rapid pace and will reach sub-10 nm dimensions in the coming years. This scaling presents many challenges, not only in terms of metrology but also in terms of the material preparation especially with respect to doping, leading to the moniker “More-than-Moore”. Current transistor technologies are based on the use of semiconductor junctions formed by the introduction of dopant atoms into the material using various methodologies and at device sizes below 10 nm, high concentration gradients become a necessity. Doping, the controlled and purposeful addition of impurities to a semiconductor, is one of the most important steps in the material preparation with uniform and confined doping to form ultra-shallow junctions at source and drain extension regions being one of the key enablers for the continued scaling of devices. Monolayer doping has shown promise to satisfy the need to conformally dope at such small feature sizes. Monolayer doping (MLD) has been shown to satisfy the requirements for extended defect-free, conformal and controllable doping on many materials ranging from the traditional silicon and germanium devices to emerging replacement materials such as III-V compounds This thesis aims to investigate the potential of monolayer doping to complement or replace conventional doping technologies currently in use in CMOS fabrication facilities across the world.

Conception, caractérisation et optimisation de SPAD en technologie Dalsa HV CMOS 0.8 μm pour intégration dans un 3D-SiPM

Résumé : Les photodiodes à avalanche monophotonique (SPAD) sont d'intérêts pour les applications requérant la détection de photons uniques avec une grande résolution temporelle, comme en physique des hautes énergies et en imagerie médicale. En fait, les matrices de SPAD, souvent appelés photomultiplicateurs sur silicium (SiPM), remplacent graduellement les tubes photomultiplicateurs (PMT) et les photodiodes à avalanche (APD). De plus, il y a une tendance à utiliser les matrices de SPAD en technologie CMOS afin d'obtenir des pixels intelligents optimisés pour la résolution temporelle. La fabrication de SPAD en technologie CMOS commerciale apporte plusieurs avantages par rapport aux procédés optoélectroniques comme le faible coût, la capacité de production, l'intégration d'électronique et la miniaturisation des systèmes. Cependant, le défaut principal du CMOS est le manque de flexibilité de conception au niveau de l'architecture du SPAD, causé par le caractère fixe et standardisé des étapes de fabrication en technologie CMOS. Un autre inconvénient des matrices de SPAD CMOS est la perte de surface photosensible amenée par la présence de circuits CMOS. Ce document présente la conception, la caractérisation et l'optimisation de SPAD fabriqués dans une technologie CMOS commerciale (Teledyne DALSA 0.8µm HV CMOS - TDSI CMOSP8G). Des modifications de procédé sur mesure ont été introduites en collaboration avec l'entreprise CMOS pour optimiser les SPAD tout en gardant la compatibilité CMOS. Les matrices de SPAD produites sont dédiées à être intégrées en 3D avec de l'électronique CMOS économique (TDSI) ou avec de l'électronique CMOS submicronique avancée, produisant ainsi un SiPM 3D numérique. Ce SiPM 3D innovateur vise à remplacer les PMT, les APD et les SiPM commerciaux dans les applications à haute résolution temporelle. L'objectif principal du groupe de recherche est de développer un SiPM 3D avec une résolution temporelle de 10 ps pour usage en physique des hautes énergies et en imagerie médicale. Ces applications demandent des procédés fiables avec une capacité de production certifiée, ce qui justifie la volonté de produire le SiPM 3D avec des technologies CMOS commerciales. Ce mémoire étudie la conception, la caractérisation et l'optimisation de SPAD fabriqués en technologie TDSI-CMOSP8G.