935 resultados para Radio Receiver Architectures
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We analyze the advantages and drawbacks of a vector delay/frequency-locked loop (VDFLL) architecture regarding the conventional scalar and the vector delay-locked loop (VDLL) architectures for GNSS receivers in harsh scenarios that include ionospheric scintillation, multipath, and high dynamics motion. The VDFLL is constituted by a bank of code and frequency discriminators feeding a central extended Kaiman filter (EKF) that estimates the receiver's position, velocity, and clock bias. Both code and frequency loops are closed vectorially through the EKF. The VDLL closes the code loop vectorially and the phase loops through individual PLLs while the scalar receiver closes both loops by means of individual independent PLLs and DLLs.
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The thesis focuses on efficient design methods and reconfiguration architectures suitable for higher performance wireless communication .The work presented in this thesis describes the development of compact,inexpensive and low power communication devices that are robust,testable and capable of handling multiple communication standards.A new multistandard Decimation Filter Design Toolbox is developed in MATLAB GUIDE environment.RNS based dual-mode decimation filters reconfigurable for WCDMA/WiMAX and WCDMA/WLANa standards are designed and implemented.It offers high speed operation with lesser area requirement and lower dynamic power dissipation.A novel sigma-delta based direct analog-to-residue converter that reduces the complexity of RNS conversion circuitry is presented.The performance of an OFDM communication system with a new RRNS-convolutional concatenated coding is analysed and improved BER performance is obtained under different channel conditions. Easily testable MAC units for filters are presented using Reed-Muller logic for realization.
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"19 January 1961."
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"8 December 1961."
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"10 February 1961."
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"27 December 1960."
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Includes index.
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"December 1977."
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In this paper new architectural approaches that improve the energy efficiency of a cellular radio access network (RAN) are investigated. The aim of the paper is to characterize both the energy consumption ratio (ECR) and the energy consumption gain (ECG) of a cellular RAN when the cell size is reduced for a given user density and service area. The paper affirms that reducing the cell size reduces the cell ECR as desired while increasing the capacity density but the overall RAN energy consumption remains unchanged. In order to trade the increase in capacity density with RAN energy consumption, without degrading the cell capacity provision, a sleep mode is introduced. In sleep mode, cells without active users are powered-off, thereby saving energy. By combining a sleep mode with a small-cell deployment architecture, the paper shows that the ECG can be increased by the factor n = (R/R) while the cell ECR continues to decrease with decreasing cell size.
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Analog-to digital Converters (ADC) have an important impact on the overall performance of signal processing system. This research is to explore efficient techniques for the design of sigma-delta ADC,specially for multi-standard wireless tranceivers. In particular, the aim is to develop novel models and algorithms to address this problem and to implement software tools which are avle to assist the designer's decisions in the system-level exploration phase. To this end, this thesis presents a framework of techniques to design sigma-delta analog to digital converters.A2-2-2 reconfigurable sigma-delta modulator is proposed which can meet the design specifications of the three wireless communication standards namely GSM,WCDMA and WLAN. A sigma-delta modulator design tool is developed using the Graphical User Interface Development Environment (GUIDE) In MATLAB.Genetic Algorithm(GA) based search method is introduced to find the optimum value of the scaling coefficients and to maximize the dynamic range in a sigma-delta modulator.
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Energy consumption in wireless networks, and in particular in cellular mobile networks, is now of major concern in respect of their potential adverse impact upon the environment and their escalating operating energy costs. The recent phenomenal growth of data services in cellular mobile networks has exacerbated the energy consumption issue and is forcing researchers to address how to design future wireless networks that take into account energy consumption constraints. One fundamental approach to reduce energy consumption of wireless networks is to adopt new radio access architectures and radio techniques. The Mobile VCE (MVCE) Green Radio project, established in 2009, is considering such new architectural and technical approaches. This paper reports highlights the key research issues pursued in the MVCE Green Radio project.
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The evolution of receiver architectures, built in modern CMOS technologies, allows the design of high efficient receivers. A key block in modern receivers is the oscillator. The main objective of this thesis is to design a very low power and low area 8-Phase Ring Oscillator for biomedical applications (ISM and WMTS bands). Oscillators with multiphase outputs and variable duty cycles are required. In this thesis we are focused in 12.5% and 50% duty-cycles approaches. The proposed circuit uses eight inverters in a ring structure, in order to generate the output duty cycle of 50%. The duty cycle of 1/8 is achieved through the combination of the longer duty cycle signals in pairs, using, for this purpose, NAND gates. Since the general application are not only the wireless communications context, as well as industrial, scientific and medical plans, the 8-Phase Oscillator is simulated to be wideband between 100 MHz and 1 GHz, and be able to operate in the ISM bands (447 MHz-930 MHz) and WMTS (600 MHz). The circuit prototype is designed in UMC 130 nm CMOS technology. The maximum value of current drawn from a DC power source of 1.2 V, at a maximum frequency of 930 MHz achieved, is 17.54 mA. After completion of the oscillator layout studied (occupied area is 165 μm x 83 μm). Measurement results confirm the expected operating range from the simulations, and therefore, that the oscillator fulfil effectively the goals initially proposed in order to be used as Local Oscillator in RF Modern Receivers.
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Modern fully integrated receiver architectures, require inductorless circuits to achieve their potential low area, low cost, and low power. The low noise amplifier (LNA), which is a key block in such receivers, is investigated in this thesis. LNAs can be either narrowband or wideband. Narrowband LNAs use inductors and have very low noise figure, but they occupy a large area and require a technology with RF options to obtain inductors with high Q. Recently, wideband LNAs with noise and distortion cancelling, with passive loads have been proposed, which can have low NF, but have high power consumption. In this thesis the main goal is to obtain a very low area, low power, and low-cost wideband LNA. First, it is investigated a balun LNA with noise and distortion cancelling with active loads to boost the gain and reduce the noise figure (NF). The circuit is based on a conventional balun LNA with noise and distortion cancellation, using the combination of a common-gate (CG) stage and common-source (CS) stage. Simulation and measurements results, with a 130 nm CMOS technology, show that the gain is enhanced by about 3 dB and the NF is reduced by at least 0.5 dB, with a negligible impact on the circuit linearity (IIP3 is about 0 dBm). The total power dissipation is only 4.8 mW, and the active area is less than 50 x 50 m2 . It is also investigated a balun LNA in which the gain is boosted by using a double feedback structure.We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with the same 130 nm CMOS technology as above, show that the gain is 24 dB and NF is less than 2.7 dB. The total power dissipation is only 5.4 mW (since no extra blocks are required), leading to a figure-of-merit (FoM) of 3.8 mW
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This paper addresses the estimation of the code-phase(pseudorange) and the carrier-phase of the direct signal received from a direct-sequence spread-spectrum satellite transmitter. Thesignal is received by an antenna array in a scenario with interferenceand multipath propagation. These two effects are generallythe limiting error sources in most high-precision positioning applications.A new estimator of the code- and carrier-phases is derivedby using a simplified signal model and the maximum likelihood(ML) principle. The simplified model consists essentially ofgathering all signals, except for the direct one, in a component withunknown spatial correlation. The estimator exploits the knowledgeof the direction-of-arrival of the direct signal and is much simplerthan other estimators derived under more detailed signal models.Moreover, we present an iterative algorithm, that is adequate for apractical implementation and explores an interesting link betweenthe ML estimator and a hybrid beamformer. The mean squarederror and bias of the new estimator are computed for a numberof scenarios and compared with those of other methods. The presentedestimator and the hybrid beamforming outperform the existingtechniques of comparable complexity and attains, in manysituations, the Cramér–Rao lower bound of the problem at hand.
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Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)