Modelo comportamental do capacitor ferroelétrico como unidade básica de neurônios artificiais e sua implementação em FPGA

This work proposes the use of the behavioral model of the hysteresis loop of the ferroelectrics capacitor as a new alternative to the usually costly techniques in the computation of nonlinear functions in artificial neurons implemented on reconfigurable hardware platform, in this case, a FPGA device. Initially the proposal has been validated by the implementation of the boolean logic through the digital models of two artificial neurons: the Perceptron and a variation of the model Integrate and Fire Spiking Neuron, both using the model also digital of the hysteresis loop of the ferroelectric capacitor as it’s basic nonlinear unit for the calculations of the neurons outputs. Finally, it has been used the analog model of the ferroelectric capacitor with the goal of verifying it’s effectiveness and possibly the reduction of the number of necessary logic elements in the case of implementing the artificial neurons on integrated circuit. The implementations has been carried out by Simulink models and the synthesizing has been done through the DSP Builder software from Altera Corporation.

Modelo de um neurônio diferenciador-integrador para representação temporal em arquiteturas conexionistas

O presente trabalho analisa diferentes modelos de representação temporal usados em arquiteturas conexionistas e propõe o uso de um novo modelo neural, chamado Neurônio Diferenciador-Integrador (NDI) para aplicação com processamento de sinais temporais. O NDI pode ser interpretado como filtro digital. Seu funcionamento exige poucos recursos computacionais e pode ser de grande valia em problemas onde a solução ideal depende de uma representação temporal instantânea, facilidade de implementação, modularidade e eliminação de ruído. Após a definição do modelo, o mesmo é sujeito a alguns experimentos teóricos utilizado em conjunto com arquiteturas conexionistas clássicas para resolver problemas que envolvem o tempo, como previsão de séries temporais, controle dinâmico e segmentação de seqüências espaço-temporais. Como conclusão, o modelo neural apresenta grande potencialidade principalmente na robótica, onde é necessário tratar os sinais sensoriais ruidosos do robô de forma rápida e econômica.

Contribuição para o estudo do embarque de uma rede neural artificial em field programmable gate array (FPGA)

This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing