75 resultados para NETTRA-PG1-FIFO


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Thesis (M. S.)--University of Illinois at Urbana-Champaign.

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Australia is experiencing an unprecedented expansion in mining due to intense demand from Asian economies thirsty for Australia’s non-renewable resources, with over $260 billion worth of capital investment currently in the pipeline (BREE 10). The scale of the present boom coupled with the longer term intensification of competitiveness in the global resources sector is changing the very nature of mining operations in Australia. Of particular note is the increasingly heavy reliance on a non-resident workforce, currently sourced from within Australia but with some recent proposals for projects to draw on overseas guest workers. This is no longer confined, as it once was, to remote, short term projects or to exploration and construction phases of operations, but is emerging as the preferred industry norm. Depending upon project location, workers may either fly-in, fly-out (FIFO) or drive-in, drive-out (DIDO), the critical point being that these operations are frequently undertaken in or near established communities. Drawing primarily on original fieldwork in one of Australia’s mining regions at the forefront of the boom, this paper explores some of the local impacts of new mining regimes, in particular their tendency to undermine collective solidarities, promote social division and fan cultural conflict.

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We present an implementation of a multicast network of processors. The processors are connected in a fully connected network and it is possible to broadcast data in a single instruction. The network works at the processor-memory speed and therefore provides a fast communication link among processors. A number of interesting architectures are possible using such a network. We show some of these architectures which have been implemented and are functional. We also show the system software calls which allow programming of these machines in parallel mode.

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本设计实现了HIRFL-CSRe同步系统控制器DSP插件内的FPGA中的FIFO(First in first out)功能,数据入口是16位DSP总线,数据出口是16位DAC总线。其核心机制采用双缓冲"乒乓操作",并在FPGA内完成一次线性插值。程序采用VHDL硬件描述语言在Altera公司的现场可编程逻辑器件ACEX1K30上实现。FIFO实现机制完全自行设计,解决了传统异步FIFO由于读写时钟异步造成的空/满标志难以准确给出及数据输出时间不能精确保证的难题,满足了HIRFL-CSRe对于输出数据不间断(每微秒一个)的要求,并由于在FPGA内实现了一次线性插值,从而把从DSP中接收到的已插值数据量增加了一倍,在宏观上降低了DSP的数据运算量。模块经现场工作证实FIFO数据输出时间误差控制在40ns内,达到设计要求。

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针对超大规模集成电路和片上系统设计中确定异步FIFO浓度的问题,根据异步FIFO运行时的属性提出FIFO动态参数模型,该模型包括FIFO饱和度、写入端和读出端数据传输率及上溢/下溢频率。在该模型的基础之上,分析异步FIFO的深度与动态参数之间的关系,采用功能仿真方法确定片上系统中异步模块之间数据传输所需FIFO的深度。对典型实例的分析表明,采用这种方法能够在保证系统数据通信性能的前提下,获得最小的FIFO深度,优化系统资源的使用。

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The recently accomplished complete genomic sequence analysis of the type strain PG1 of Mycoplasma mycoides subsp. mycoides small-colony type revealed four large repeated segments of 24, 13, 12, and 8 kb that are flanked by insertion sequence (IS) elements. Genetic analysis of type strain PG1 and African, European, and Australian field and vaccine strains revealed that the 24-kb genetic locus is repeated only in PG1 and not in other M. mycoides subsp. mycoides SC strains. In contrast, the 13-kb genetic locus was found duplicated in some strains originating from Africa and Australia but not in strains that were isolated from the European outbreaks. The 12- and 8-kb genetic loci were found in two and three copies, respectively, in all 28 strains analyzed. The flanking IS elements are assumed to lead to these tandem duplications, thus contributing to genomic plasticity. This aspect must be considered when designing novel diagnostic approaches and recombinant vaccines.