Models and methods for power monolithic microwave integrated circuits

Computer aided design of Monolithic Microwave Integrated Circuits (MMICs) depends critically on active device models that are accurate, computationally efficient, and easily extracted from measurements or device simulators. Empirical models of active electron devices, which are based on actual device measurements, do not provide a detailed description of the electron device physics. However they are numerically efficient and quite accurate. These characteristics make them very suitable for MMIC design in the framework of commercially available CAD tools. In the empirical model formulation it is very important to separate linear memory effects (parasitic effects) from the nonlinear effects (intrinsic effects). Thus an empirical active device model is generally described by an extrinsic linear part which accounts for the parasitic passive structures connecting the nonlinear intrinsic electron device to the external world. An important task circuit designers deal with is evaluating the ultimate potential of a device for specific applications. In fact once the technology has been selected, the designer would choose the best device for the particular application and the best device for the different blocks composing the overall MMIC. Thus in order to accurately reproducing the behaviour of different-in-size devices, good scalability properties of the model are necessarily required. Another important aspect of empirical modelling of electron devices is the mathematical (or equivalent circuit) description of the nonlinearities inherently associated with the intrinsic device. Once the model has been defined, the proper measurements for the characterization of the device are performed in order to identify the model. Hence, the correct measurement of the device nonlinear characteristics (in the device characterization phase) and their reconstruction (in the identification or even simulation phase) are two of the more important aspects of empirical modelling. This thesis presents an original contribution to nonlinear electron device empirical modelling treating the issues of model scalability and reconstruction of the device nonlinear characteristics. The scalability of an empirical model strictly depends on the scalability of the linear extrinsic parasitic network, which should possibly maintain the link between technological process parameters and the corresponding device electrical response. Since lumped parasitic networks, together with simple linear scaling rules, cannot provide accurate scalable models, either complicate technology-dependent scaling rules or computationally inefficient distributed models are available in literature. This thesis shows how the above mentioned problems can be avoided through the use of commercially available electromagnetic (EM) simulators. They enable the actual device geometry and material stratification, as well as losses in the dielectrics and electrodes, to be taken into account for any given device structure and size, providing an accurate description of the parasitic effects which occur in the device passive structure. It is shown how the electron device behaviour can be described as an equivalent two-port intrinsic nonlinear block connected to a linear distributed four-port passive parasitic network, which is identified by means of the EM simulation of the device layout, allowing for better frequency extrapolation and scalability properties than conventional empirical models. Concerning the issue of the reconstruction of the nonlinear electron device characteristics, a data approximation algorithm has been developed for the exploitation in the framework of empirical table look-up nonlinear models. Such an approach is based on the strong analogy between timedomain signal reconstruction from a set of samples and the continuous approximation of device nonlinear characteristics on the basis of a finite grid of measurements. According to this criterion, nonlinear empirical device modelling can be carried out by using, in the sampled voltage domain, typical methods of the time-domain sampling theory.

Variable 360° Vector-Sum Phase Shifter With Coarse and Fine Vector Scaling

A CMOS vector-sum phase shifter covering the full 360° range is presented in this paper. Broadband operational transconductance amplifiers with variable transconductance provide coarse scaling of the quadrature vector amplitudes. Fine scaling of the amplitudes is accomplished using a passive resistive network. Expressions are derived to predict the maximum bit resolution of the phase shifter from the scaling factor of the coarse and fine vector-scaling stages. The phase shifter was designed and fabricated using the standard 130-nm CMOS process and was tested on-wafer over the frequency range of 4.9–5.9 GHz. The phase shifter delivers root mean square (rms) phase and amplitude errors of 1.25° and 0.7 dB, respectively, at the midband frequency of 5.4 GHz. The input and output return losses are both below 17 dB over the band, and the insertion loss is better than 4 dB over the band. The circuit uses an area of 0.303 mm2 excluding bonding pads and draws 28 mW from a 1.2 V supply.

Broadband RF current detector

The problems to be solved in this thesis were 1) development of a broadband RF preamplifier to be used with non-ferrous current probes so that the amplified signal exceeds the errors due to cable pickup, no detection is needed in this application, and 2) development of a self-contained device that amplifies and detects the output from a nonferrous current probe, providing a digital readout of the current. These instruments have been completed and are being tested for use by the National Institutes of Occupational Safety and Health (NIOSH). The self-contained current meter operates at frequencies up to 600 MHz, and detects currents as low as 8 mA . At these current magnitudes, the probe (pick-up coil) will output a voltage of 500μV (-53 dBm on 50Ω) which will have to be raised above 0 dBm. The final circuit uses a RF mixer as a variable attenuator in order to increase the dynamic range, two Monolithic Microwave Integrated Circuits (MMIC) for preamplification, a final broadband amplifier to raise the output compression point, a Schottky diode detector, a sample and hold circuit, and a liquid crystal digital panel meter.

A new chemorheological analysis of highly filled thermosets used in integrated circuit packaging

Chemorheology (and thus process modeling) of highly filled thermosets used in integrated circuit (IC) packaging has been complicated by their highly filled nature, fast kinetics of curing, and viscoelastic nature. This article summarizes a more thorough chemorheological analysis of a typical IC packaging thermoset material, including novel isothermal and nonisothermal multiwave parallel-plate chemorheology. This new chemorheological analysis may be used to optimize existing and design new IC packaging processes. (C) 1997 John Wiley & Sons, Inc.

Arrays of gold microelectrodes made from split integrated circuit chips

A simple and inexpensive way to fabricate arrays of gold microelectrodes is proposed. Integrated circuit chips are sawed through their middle, normal to the longest axis, leading to destruction of the silicon circuit and rupture of the gold wires that interconnect it with the external terminals. Polishing the resulting rough surface converts the tips of the wires embedded in the chip halves into arrays of gold microdisks of about 25 mu m diameter. The number of active microelectrodes (MEs), of an array depends on the number of pins in the chip, n, being typically (n/2)-4. These MEs can be used individually or externally interconnected in any combination. X-ray images of the chips and micrographs of the resulting surface of the polished arrays have revealed variable distances between neighbor MEs, which are, however, larger than 10 times the radius of the disks. This feature of the MEs prevents diffusional cross-talk between electrodes. The use of these microdisk electrodes for analytical purposes exhibits sigmoidal voltammograms, and chronoamperometric experiments confirm the nonlinear i vs. t(1/2) plots, typical for processes where radial diffusion prevails. Satisfactory uniformity was observed for the response of each electrode of an array, indicating similarity of geometry and disk areas. The potentialities of these MEs were demonstrated by the determination of cadmium at ppb levels using square wave voltammetry with preconcentration. Due to the relative ease with which these MEs can be manufactured and their good performance in (chemical) analysis, wide applications in electrochemistry and electroanalysis is envisioned.

Flow-through cell based on an array of gold microelectrodes obtained from modified integrated circuit chips

The construction of a flow-through cell incorporating an array of gold microelectrodes is described and its application to flow injection analysis with amperometric detection is presented, Simple modification of almost any conventional integrated circuit chip, used as an inexpensive source of pre-assembled gold micro-wires, leads to the rapid and successful preparation of arrays of 8-48 elements, the polymeric encapsulation material from the top face of the chip is removed by abrasion until the gold micro-mires (used to interconnect the silicon circuit to the external contact pins of the chip) are disrupted and their transversal (elliptical) sections become exposed. Once polished, the flat and smooth top surface of the gold microelectrode-array chip (MEAC) is provided with a spacer and fitted under pressure against an acrylic block with the reference and auxiliary electrodes, to form the electrochemical (thin-layer) flow cell, while the contact pins are plugged into a standard IC socket, This design ensures autonomous electric contact with each electrode and allows fast dismantling for polishing or substitution, the performance of flow cells with MEACs was investigated utilizing the technique of reverse pulse amperometry without oxygen removal, A method was established for the determination of the copper concentration in sugar cane spirit, regulated by law for beverages, Samples from industrial producers and small-scale (alembic) brewers were compared, With a 24 MEAC, a detection limit of 30 mu g I-l of copper (4.7 x 10(-7) mol l(-1) of Cu-II for 100 mu l injections) was calculated, Routine operation was established at a frequency of 60-90 determinations per hour, Intercomparison with atomic absorption spectrometric determinations resulted in excellent agreement.

Design of a LNA and a Gilbert Cell Mixer MMICs with a GaAs PHEMT technology

The design of a Gilbert Cell Mixer and a low noise amplifier (LNA), using GaAs PHEMT technology is presented. The compatibility is shown for co-integration of both block on the same chip, to form a high performance 1.9 GHz receiver front-end. The designed LNA shows 9.23 dB gain and 2.01 dB noise figure (NF). The mixer is designed to operate at RF=1.9 GHz, LO=2.0 GHz and IF=100 MHz with a gain of 14.3 dB and single sideband noise figure (SSB NF) of 9.6 dB. The mixer presents a bandwith of 8 GHz.

Accurate linewidth measurements on integrated-circuit photomasks /

"Supported by the Defense Advanced Research Projects Agency ... and the National Bureau of Standards."

Chemical studies of plasma etchants used in integrated circuit manufacture

Plasma or "dry" etching is an essential process for the production of modern microelectronic circuits. However, despite intensive research, many aspects of the etch process are not fully understood. The results of studies of the plasma etching of Si and Si02 in fluorine-containing discharges, and the complementary technique of plasma polymerisation are presented in this thesis. Optical emission spectroscopy with argon actinometry was used as the principle plasma diagnostic. Statistical experimental design was used to model and compare Si and Si02 etch rates in CF4 and SF6 discharges as a function of flow, pressure and power. Etch mechanisms m both systems, including the potential reduction of Si etch rates in CF4 due to fluorocarbon polymer formation, are discussed. Si etch rates in CF4 /SF6 mixtures were successfully accounted for by the models produced. Si etch rates in CF4/C2F6 and CHF3 as a function of the addition of oxygen-containing additives (02, N20 and CO2) are shown to be consistent with a simple competition between F, 0 and CFx species for Si surface sites. For the range of conditions studied, Si02 etch rates were not dependent on F-atom concentration, but the presence of fluorine was essential in order to achieve significant etch rates. The influence of a wide range of electrode materials on the etch rate of Si and Si02 in CF4 and CF4 /02 plasmas was studied. It was found that the Si etch rate in a CF4 plasma was considerably enhanced, relative to an anodised aluminium electrode, in the presence of soda glass or sodium or potassium "doped" quartz. The effect was even more pronounced in a CF4 /02 discharge. In the latter system lead and copper electrodes also enhanced the Si etch rate. These results could not be accounted for by a corresponding rise in atomic fluorine concentration. Three possible etch enhancement mechanisms are discussed. Fluorocarbon polymer deposition was studied, both because of its relevance to etch mechanisms and its intrinsic interest, as a function of fluorocarbon source gas (CF4, C2F6, C3F8 and CHF3), process time, RF power and percentage hydrogen addition. Gas phase concentrations of F, H and CF2 were measured by optical emission spectroscopy, and the resultant polymer structure determined by X-ray photoelectron spectroscopy and infrared spectroscopy. Thermal and electrical properties were measured also. Hydrogen additions are shown to have a dominant role in determining deposition rate and polymer composition. A qualitative description of the polymer growth mechanism is presented which accounts for both changes in growth rate and structure, and leads to an empirical deposition rate model.

Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design

To tackle the challenges at circuit level and system level VLSI and embedded system design, this dissertation proposes various novel algorithms to explore the efficient solutions. At the circuit level, a new reliability-driven minimum cost Steiner routing and layer assignment scheme is proposed, and the first transceiver insertion algorithmic framework for the optical interconnect is proposed. At the system level, a reliability-driven task scheduling scheme for multiprocessor real-time embedded systems, which optimizes system energy consumption under stochastic fault occurrences, is proposed. The embedded system design is also widely used in the smart home area for improving health, wellbeing and quality of life. The proposed scheduling scheme for multiprocessor embedded systems is hence extended to handle the energy consumption scheduling issues for smart homes. The extended scheme can arrange the household appliances for operation to minimize monetary expense of a customer based on the time-varying pricing model.

A 5GHz/1.8V CMOS Active Balun Integrated with LNA

The development of high performance monolithic RF front-ends requires innovative RF circuit design to make the best of a good technology. A fully differential approach is usually preferred, due to its well-known properties. Although the differential approach must be preserved inside the chip, there are cases where the input signal is single-ended such as RF image filters and IF filters in a RF receiver. In these situations, a stage able to convert single-ended into differential signals (balun) is needed. The most cited topology, which is capable of providing high gain, consists on a differential stage with one of the two inputs grounded. Unfortunately, this solution has some drawbacks when implemented monolithically. This work presents the design and simulated results of an innovative high-performance monolithic single to differential converter, which overcomes the limitations of the circuits.The integration of the monolithic active balun circuit with an LNA on a 0.18μm CMOS process is also reported. The circuits presented here are aimed at 802.11a. Section 2 describes the balun circuit and section 3 presents its performance when it is connected to a conventional single-ended LNA. Section 4 shows the simulated performance results focused at phase/amplitude balance and noise figure. Finally, the last section draws conclusions and future work.

A physical frequency-dependent compact model for RF integrated inductors

A frequency-dependent compact model for inductors in high ohmic substrates, which is based on an energy point-of-view, is developed. This approach enables the description of the most important coupling phenomena that take place inside the device. Magnetically induced losses are quite accurately calculated and coupling between electric and magnetic fields is given by means of a delay constant. The later coupling phenomenon provides a modified procedure for the computation of the fringing capacitance value, when the self-resonance frequency of the inductor is used as a fitting parameter. The model takes into account the width of every metal strip and the pitch between strips. This enables the description of optimized layout inductors. Data from experiments and electromagnetic simulators are presented to test the accuracy of the model.

Improvement of the quality factor of RF integrated inductors by layout optimization

A systematic method to improve the quality (Q) factor of RF integrated inductors is presented in this paper. The proposed method is based on the layout optimization to minimize the series resistance of the inductor coil, taking into account both ohmic losses, due to conduction currents, and magnetically induced losses, due to eddy currents. The technique is particularly useful when applied to inductors in which the fabrication process includes integration substrate removal. However, it is also applicable to inductors on low-loss substrates. The method optimizes the width of the metal strip for each turn of the inductor coil, leading to a variable strip-width layout. The optimization procedure has been successfully applied to the design of square spiral inductors in a silicon-based multichip-module technology, complemented with silicon micromachining postprocessing. The obtained experimental results corroborate the validity of the proposed method. A Q factor of about 17 have been obtained for a 35-nH inductor at 1.5 GHz, with Q values higher than 40 predicted for a 20-nH inductor working at 3.5 GHz. The latter is up to a 60% better than the best results for a single strip-width inductor working at the same frequency.

High performance terahertz resonant tunnelling diode sources and broadband antenna for air-side radiation

Resonant tunnelling diode (RTD) is known to be the fastest electronics device that can be fabricated in compact form and operate at room temperature with potential oscillation frequency up to 2.5 THz. The RTD device consists of a narrow band gap quantum well layer sandwiched between two thin wide band gap barriers layers. It exhibits negative differential resistance (NDR) region in its current-voltage (I-V) characteristics which is utilised in making oscillators. Up to date, the main challenge is producing high output power at high frequencies in particular. Although oscillation frequencies of ~ 2 THz have been already reported, the output power is in the range of micro-Watts. This thesis describes the systematic work on the design, fabrication, and characterisation of RTD-based oscillators in microwave/millimetre-wave monolithic integrated circuits (MMIC) form that can produce high output power and high oscillation frequency at the same time. Different MMIC RTD oscillator topologies were designed, fabricated, and characterised in this project which include: single RTD oscillator which employs one RTD device, double RTDs oscillator which employs two RTD devices connected in parallel, and coupled RTD oscillators which combine the powers of two oscillators over a single load, based on mutual coupling and which can employ up to four RTD devices. All oscillators employed relatively large size RTD devices for high power operation. The main challenge was to realise high oscillation frequency (~ 300 GHz) in MMIC form with the employed large sized RTD devices. To achieve this aim, proper designs of passive structures that can provide small values of resonating inductances were essential. These resonating inductance structures included shorted coplanar wave guide (CPW) and shorted microstrip transmission lines of low characteristics impedances Zo. Shorted transmission line of lower Zo has lower inductance per unit length. Thus, the geometrical dimensions would be relatively large and facilitate fabrication by low cost photolithography. A series of oscillators with oscillation frequencies in the J-band (220 – 325 GHz) range and output powers from 0.2 – 1.1 mW have been achieved in this project, and all were fabricated using photolithography. Theoretical estimation showed that higher oscillation frequencies (> 1 THz) can be achieved with the proposed MMIC RTD oscillators design in this project using photolithography with expected high power operation. Besides MMIC RTD oscillators, reported planar antennas for RTD-based oscillators were critically reviewed and the main challenges in designing high performance integrated antennas on large dielectric constant substrates are discussed in this thesis. A novel antenna was designed, simulated, fabricated, and characterised in this project. It was a bow-tie antenna with a tuning stub that has very wide bandwidth across the J-band. The antenna was diced and mounted on a reflector ground plane to alleviate the effect of the large dielectric constant substrate (InP) and radiates upwards to the air-side direction. The antenna was also investigated for integration with the all types of oscillators realised in this project. One port and two port antennas were designed, simulated, fabricated, and characterised and showed the suitability of integration with the single/double oscillator layout and the coupled oscillator layout, respectively.

A current-mode interface circuit for a piezoresistive pressure sensor

An interfacing circuit for piezoresistive pressure sensors based on CMOS current conveyors is presented. The main advantages of the proposed interfacing circuit include the use of a single piezoresistor, the capability of offset compensation, and a versatile current-mode configuration, with current output and current or voltage input. Experimental tests confirm linear relation of output voltage versus piezoresistance variation.