McKinnon Columbus Chain Limited Records 1948, 1958-1960, 1963-1969, 1971, 1974-1975, 1978, n.d.

Ontario Editorial Bureau (O.E.B.)

Rock Hill Hardware Company Records - Accession 220

The Rock Hill Hardware Company was organized on June 4, 1893 by A.R. Smith and John Gelzer, A.A. Barron and his sons R.E. and W.L. bought Smith out in 1896 and by 1907 had acquired the whole firm. The Barron family owned and operated it until it closed in 1978. The collection consists of a 1906 ledger, financial records, a photograph, a seed license, World War II ration booklets, and newspaper clippings.

Furniture of the Pilgrim century, 1620-1720, including colonial utensils and hardware,

Mode of access: Internet.

Power network in loop : a paradigm for real-time simulation and hardware testing

This paper discusses a new paradigm of real-time simulation of power systems in which equipment can be interfaced with a real-time digital simulator. In this scheme, one part of a power system can be simulated by using a real-time simulator; while the other part is implemeneted as a physical system. The only interface of the physical system with the computer-based simulator is through data-acquisition system. The physical system is driven by a voltage-source converter (VSC)that mimics the power system simulated in the real-time simulator. In this papar, the VSC operates in a voltage-control mode to track the point of common coupling voltage signal supplied by the digital simulator. This type of splitting a network in two parts and running a real-time simulation with a physical system in parallel is called a power network in loop here. this opens up the possibility of study of interconnection o f one or several distributed generators to a complex power network. The proposed implementation is verified through simulation studies using PSCAD/EMTDC and through hardware implementation on a TMS320G2812 DSP.

USHA: unified software and hardware architecture for video decoding

Video decoders used in emerging applications need to be flexible to handle a large variety of video formats and deliver scalable performance to handle wide variations in workloads. In this paper we propose a unified software and hardware architecture for video decoding to achieve scalable performance with flexibility. The light weight processor tiles and the reconfigurable hardware tiles in our architecture enable software and hardware implementations to co-exist, while a programmable interconnect enables dynamic interconnection of the tiles. Our process network oriented compilation flow achieves realization agnostic application partitioning and enables seamless migration across uniprocessor, multi-processor, semi hardware and full hardware implementations of a video decoder. An application quality of service aware scheduler monitors and controls the operation of the entire system. We prove the concept through a prototype of the architecture on an off-the-shelf FPGA. The FPGA prototype shows a scaling in performance from QCIF to 1080p resolutions in four discrete steps. We also demonstrate that the reconfiguration time is short enough to allow migration from one configuration to the other without any frame loss.

An investigation into the information exchange between a consultant and client company: a case study

This report deals with collaborations of engineering consultants and clients in the automobile industry.

In these relationships three main challenges have been identified which have to be addressed by the consultancies. Therefore, the research takes the viewpoint of the consulting side. The challenges are

(i) the appropriate project goal definition;

(ii) achieving client satisfaction; and

(iii) dealing with international clients.

An investigation of such a relationship carried out on a case study shows that improvements can be achieved through communication support. The ways to do that are proposed.

Architecture research and hardware implementation on simplified neural computing system for face identification

This paper describes a special-purpose neural computing system for face identification. The system architecture and hardware implementation are introduced in detail. An algorithm based on biomimetic pattern recognition has been embedded. For the total 1200 tests for face identification, the false rejection rate is 3.7% and the false acceptance rate is 0.7%.

FPGA Soft-core Processors, Compiler and Hardware Optimizations validated using HOG

There is demand for an easily programmable, high performance image processing platform based on FPGAs. In previous work, a novel, high performance processor - IPPro was developed and a Histogram of Orientated Gradients (HOG) algorithm study undertaken on a Xilinx Zynq platform. Here, we identify and explore a number of mapping strategies to improve processing efficiency for soft-cores and a number of options for creation of a division coprocessor. This is demonstrated for the revised high definition HOG implementation on a Zynq platform, resulting in a performance of 328 fps which represents a 146% speed improvement over the original realization and a tenfold reduction in energy.

Shares Certificate - Gladstone Mines and Reduction Company

A shares certificate for Gladstone Mines and Reduction Company in the amount of 200 shares. The certificate is dated 13 March 1925 and is signed by the secretary F.J. Carr and the president Charles Stoddart. The price is one dollar per share and it is made out to W.H. Cowan.

Certificate for One Share of Capital Stock in Nicola Valley Coal and Coke Company

Certificate for 1 share of capital stock in Nicola Valley Coal and Coke Company to Welland D. Woodruff, May 13, 1905.