Use of macros in backtrack programming /

Thesis (M.S.)--University of Illinois at Urbana-Champaign.

Calculation of construction schedules and priorities with the aid of electronic computers,

Cover title.

Accuracy of turbulence models and CFD for thermal characterisation of electronic systems

A major percentage of the heat emitted from electronic packages can be extracted by air cooling whether by means of natural or forced convection. This flow of air throughout an electronic system and the heat extracted is highly dependable on the nature of turbulence present in the flow field. This paper will discuss results from an investigation into the accuracy of turbulence models to predict air cooling for electronic packages and systems.

Investigation into the performance of turbulence models for fluid flow and heat transfer phenomena in electronic applications

Computational Fluid Dynamics (CFD) is gradually becoming a powerful and almost essential tool for the design, development and optimization of engineering applications. However the mathematical modelling of the erratic turbulent motion remains the key issue when tackling such flow phenomena. The reliability of CFD analysis depends heavily on the turbulence model employed together with the wall functions implemented. In order to resolve the abrupt changes in the turbulent energy and other parameters situated at near wall regions a particularly fine mesh is necessary which inevitably increases the computer storage and run-time requirements. Turbulence modelling can be considered to be one of the three key elements in CFD. Precise mathematical theories have evolved for the other two key elements, grid generation and algorithm development. The principal objective of turbulence modelling is to enhance computational procedures of efficient accuracy to reproduce the main structures of three dimensional fluid flows. The flow within an electronic system can be characterized as being in a transitional state due to the low velocities and relatively small dimensions encountered. This paper presents simulated CFD results for an investigation into the predictive capability of turbulence models when considering both fluid flow and heat transfer phenomena. Also a new two-layer hybrid kε / kl turbulence model for electronic application areas will be presented which holds the advantages of being cheap in terms of the computational mesh required and is also economical with regards to run-time.

Analyzing the performance of flexible substrates for lead-free applications

The performance of flexible substrates for lead-free applications was studied using finite element method (FEM). Firstly, the thermal induced stress in the flex substrate during the lead free solder reflow process was predicted. The shear stress at the interface between the copper track and flex was plotted. This shear stress increases with the thickness of the copper track and the thickness of the flex. Secondly, an anisotropic conductive film (ACF) flip chip was taken as a typical lead-free application of the flex substrate and the moisture effect on the reliability of ACF joints were studied using a 3D macro-micro modeling technique. It is found that the time to be saturated of an ACF flip chip is much dependent on the moisture diffusion rate in the polyimide substrate. The majority moisture diffuses into the ACF layer from the substrate side rather than the periphery of the ACF. The moisture induced stress was predicted and the predominant tensile stress was found at the interface between the conductive particle and metallization which could reduce the contact area and even cause the electrical failure

Thermal-mechanical modelling of power electronic module packaging

In this paper the reliability of the isolation substrate and chip mountdown solder interconnect of power modules under thermal-mechanical loading has been analysed using a numerical modelling approach. The damage indicators such as the peel stress and the accumulated plastic work density in solder interconnect are calculated for a range of geometrical design parameters, and the effects of these parameters on the reliability are studied by using a combination of the finite element analysis (FEA) method and optimisation techniques. The sensitivities of the reliability of the isolation substrate and solder interconnect to the changes of the design parameters are obtained and optimal designs are studied using response surface approximation and gradient optimization method

Wire bond reliability for power electronic modules - effect of bonding temperature

In this paper, thermal cycling reliability along with ANSYS analysis of the residual stress generated in heavy-gauge Al bond wires at different bonding temperatures is reported. 99.999% pure Al wires of 375 mum in diameter, were ultrasonically bonded to silicon dies coated with a 5mum thick Al metallisation at 25degC (room temperature), 100degC and 200degC, respectively (with the same bonding parameters). The wire bonded samples were then subjected to thermal cycling in air from -60degC to +150degC. The degradation rate of the wire bonds was assessed by means of bond shear test and via microstructural characterisation. Prior to thermal cycling, the shear strength of all of the wire bonds was approximately equal to the shear strength of pure aluminum and independent of bonding temperature. During thermal cycling, however, the shear strength of room temperature bonded samples was observed to decrease more rapidly (as compared to bonds formed at 100degC and 200degC) as a result of a high crack propagation rate across the bonding area. In addition, modification of the grain structure at the bonding interface was also observed with bonding temperature, leading to changes in the mechanical properties of the wire. The heat and pressure induced by the high temperature bonding is believed to promote grain recovery and recrystallisation, softening the wires through removal of the dislocations and plastic strain energy. Coarse grains formed at the bonding interface after bonding at elevated temperatures may also contribute to greater resistance for crack propagation, thus lowering the wire bond degradation rate

Reliability of power electronic modules

The electric car, the all electric aircraft and requirements for renewable energy are examples of potential technologies needed to address the world problem of global warming/carbon emission etc. Power electronics and packaged modules are fundamental for the underpinning of these technologies and with the diverse requirements for electrical configurations and the range of environmental conditions, time to market is paramount for module manufacturers and systems designers alike. This paper details some of the results from a major UK project into the reliability of power electronic modules using physics of failure techniques. This paper presents a design methodology together with results that demonstrate enhanced product design with improved reliability, performance and value within acceptable time scales

Predicting the reliability of power electronic modules

This paper discusses the reliability of an IGBT power electronics module. This work is part of a major UK funded initiative into the design, packaging and reliability of power electronic modules. The predictive methodology combines numerical modeling techniques with experimentation and accelerated testing to identify failure modes and mechanisms for these type of power electronic module structures. The paper details results for solder joint failure substrate solder. Finite element method modeling techniques have been used to predict the stress and strain distribution within the module structures. Together with accelerated life testing, these results have provided a failure model for these joints which has been used to predict reliability of a rail traction application

High current density induced damage mechanisms in electronic solder joints: a state-of-the-art review

High current density induced damages such as electromigration in the on-chip interconnection /metallization of Al or Cu has been the subject of intense study over the last 40 years. Recently, because of the increasing trend of miniaturization of the electronic packaging that encloses the chip, electromigration as well as other high current density induced damages are becoming a growing concern for off-chip interconnection where low melting point solder joints are commonly used. Before long, a huge number of publications have been explored on the electromigration issue of solder joints. However, a wide spectrum of findings might confuse electronic companies/designers. Thus, a review of the high current induced damages in solder joints is timely right this moment. We have selected 6 major phenomena to review in this paper. They are (i) electromigration (mass transfer due electron bombardment), (ii) thermomigration (mass transfer due to thermal gradient), (iii) enhanced intermetallic compound growth, (iv) enhanced current crowding, (v) enhanced under bump metallisation dissolution and (vi) high Joule heating and (vii) solder melting. the damage mechanisms under high current stressing in the tiny solder joint, mentioned in the review article, are significant roadblocks to further miniaturization of electronics. Without through understanding of these failure mechanisms by experiments coupled with mathematical modeling work, further miniaturization in electronics will be jeopardized

Parallel patterns + Macro Data Flow for multi-core programming

Data flow techniques have been around since the early '70s when they were used in compilers for sequential languages. Shortly after their introduction they were also consideredas a possible model for parallel computing, although the impact here was limited. Recently, however, data flow has been identified as a candidate for efficient implementation of various programming models on multi-core architectures. In most cases, however, the burden of determining data flow "macro" instructions is left to the programmer, while the compiler/run time system manages only the efficient scheduling of these instructions. We discuss a structured parallel programming approach supporting automatic compilation of programs to macro data flow and we show experimental results demonstrating the feasibility of the approach and the efficiency of the resulting "object" code on different classes of state-of-the-art multi-core architectures. The experimental results use different base mechanisms to implement the macro data flow run time support, from plain pthreads with condition variables to more modern and effective lock- and fence-free parallel frameworks. Experimental results comparing efficiency of the proposed approach with those achieved using other, more classical, parallel frameworks are also presented. © 2012 IEEE.

The use of computers in engineering education; report. 1st-3d; 1960-62.

Cover title, 1960: Electronic computers in engineering education; report.

Linear system solvers for parallel computers /

Includes bibliographical references.

Improving the performance of virtual memory computers /

"UILU-ENG 78 1741."