Low-intensity differential photocapacitance of MOS structures

Some new observations on the phenomenon of photocapacitane on n-type silicon MOS structures under low intensities of illumination are reported. The difference between the illuminated and dark C---characteristics is automatically followed as a function of the applied bias thereby obtaining the differential photocapacitance and the resulting characteristics has been termed as the Low Intensity Differential Photocapacitance (LIDP). For an MOS capacitor, the LIDP characteristics is seen to go through a well defined maximum. The phenomenon has been investigated under different ambient conditions like light intensity, temperature, dependance of the frequency of the light etc. and it has been found that the phenomenon is due to a band excband excitation. In this connection, a novel sensitive technique for the measurement of the capacitance based upon following the frequency changes of a tank circuit is also described in some detail. It is also shown that the phenomenon can be understood by a simple theoretical model.

I–U Characteristics of MOS Structures on Polycrystalline Silicon

Current-voltage (I–U) characteristics of MOS structures on polycrystalline silicon are investigated. A model based on the carrier transport through the traps in the oxide is described to explain the I–U characteristics.Es werden Strom-Spannungs(I–U)-Charakteristiken von MOS-Strukturen auf polykristallinem Silizium untersucht. Ein Modell zur Erklärung der I–U-Charakteristiken wird beschrieben, das auf dem Ladungstransport über Oxidtraps beruht.

High performance sol-gel spin-coated titanium dioxide dielectric based MOS structures

High-kappa TiO2 thin films have been fabricated using cost effective sol-gel and spin-coating technique on p-Si (100) wafer. Plasma activation process was used for better adhesion between TiO2 films and Si. The influence of annealing temperature on the structure-electrical properties of titania films were investigated in detail. Both XRD and Raman studies indicate that the anatase phase crystallizes at 400 degrees C, retaining its structural integrity up to 1000 degrees C. The thickness of the deposited films did not vary significantly with the annealing temperature, although the refractive index and the RMS roughness enhanced considerably, accompanied by a decrease in porosity. For electrical measurements, the films were integrated in metal-oxide-semiconductor (MOS) structure. The electrical measurements evoke a temperature dependent dielectric constant with low leakage current density. The Capacitance-voltage (C-V) characteristics of the films annealed at 400 degrees C exhibited a high value of dielectric constant (similar to 34). Further, frequency dependent C-V measurements showed a huge dispersion in accumulation capacitance due to the presence of TiO2/Si interface states and dielectric polarization, was found to follow power law dependence on frequency (with exponent `s'=0.85). A low leakage current density of 3.6 x 10(-7) A/cm(2) at 1 V was observed for the films annealed at 600 degrees C. The results of structure-electrical properties suggest that the deposition of titania by wet chemical method is more attractive and cost-effective for production of high-kappa materials compared to other advanced deposition techniques such as sputtering, MBE, MOCVD and AID. The results also suggest that the high value of dielectric constant kappa obtained at low processing temperature expands its scope as a potential dielectric layer in MOS device technology. (C) 2015 Elsevier Ltd. All rights reserved.

DLTS analysis of amphoteric interface defects in high-TiO2 MOS structures prepared by sol-gel spin-coating

High-kappa TiO2 thin films have been fabricated from a facile, combined sol-gel spin - coating technique on p and n type silicon substrate. XRD and Raman studies headed the existence of anatase phase of TiO2 with a small grain size of 18 nm. The refractive index `n' quantified from ellipsometry is 2.41. AFM studies suggest a high quality, pore free films with a fairly small surface roughness of 6 angstrom. The presence of Ti in its tetravalent state is confirmed by XPS analysis. The defect parameters observed at the interface of Si/TiO2 were studied by capacitance - voltage (C - V) and deep level transient spectroscopy (DLTS). The flat - band voltage (V-FB) and the density of slow interface states estimated are -0.9, -0.44 V and 5.24x10(10), 1.03x10(11) cm(-2); for the NMOS and PMOS capacitors, respectively. The activation energies, interface state densities and capture cross -sections measured by DLTS are E-V + 0.30, E-C - 0.21 eV; 8.73x10(11), 6.41x10(11) eV(-1) cm(-2) and 5.8x10(-23), 8.11x10(-23) cm(2) for the NMOS and PMOS structures, respectively. A low value of interface state density in both P-and N-MOS structures makes it a suitable alternate dielectric layer for CMOS applications. And also very low value of capture cross section for both the carriers due to the amphoteric nature of defect indicates that the traps are not aggressive recombination centers and possibly can not contribute to the device operation to a large extent. (C) 2015 Author(s).

Progress in the understanding of Ni silicide formation for advanced MOS structures

Metallic silicides have been used as contact materials on source/drain and gate in metal-oxide semiconductor (MOS) structure for 40 years. Since the 65 nm technology node, NiSi is the preferred material for contact in microelectronic due to low resistivity, low thermal budget, and low Si consumption. Ni(Pt)Si with 10 at.% Pt is currently employed in recent technologies since Pt allows to stabilize NiSi at high temperature. The presence of Pt and the very low thickness (<10 nm) needed for the device contacts bring new concerns for actual devices. In this work, in situ techniques [X-ray diffraction (XRD), X-ray reflectivity (XRR), sheet resistance, differential scanning calorimetry (DSC)] were combined with atom probe tomography (APT) to study the formation mechanisms as well as the redistribution of dopants and alloy elements (Pt, Pd.) during the silicide formation. Phenomena like nucleation, lateral growth, interfacial reaction, diffusion, precipitation, and transient phase formation are investigated. The effect of alloy elements (Pt, Pd.) and dopants (As, B.) as well as stress and defects induced by the confinement in devices on the silicide formation mechanism and alloying element redistribution is examined. In particular APT has been performed for the three-dimensional (3D) analysis of MOSFET at the atomic scale. The advances in the understanding of the mechanisms of formation and redistribution are discussed. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Homoepitaxial growth and MOS structures of 4H-SiC on off oriented n-type (0001)Si-faces

Homoepitaxial growth of 4H-SiC on off-oriented n-type Si-face (0001) substrates was performed in a home-made hot-wall low pressure chemical vapor deposition (LPCVD) reactor with SiH4 and C2H4 at temperature of 1500 C and pressure of 20 Torr. The surface morphology and intentional in-situ NH3 doping in 4H-SiC epilayers were investigated by using atomic force microscopy (AFM) and secondary ion mass spectroscopy (SIMS). Thermal oxidization of 4H-SiC homoepitaxial layers was conducted in a dry O-2 and H-2 atmosphere at temperature of 1150 C. The oxide was investigated by employing x-ray photoelectron spectroscopy (XPS). 4H-SiC MOS structures were obtained and their C-V characteristics were presented.

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Impedance‐frequency characteristics of metal‐oxide‐semiconductor structures on polycrystalline silicon

This paper reports the variations in impedance with frequency of metal‐oxide‐semiconductor (MOS) structures on polycrystalline silicon. The origin of these impedance‐frequency characteristics are qualitatively explained. These characteristics indicate that the MOS structure on polycrystalline silicon can be exploited to realize voltage controlled filters.

Liquid phase epitaxial growth of pure and doped GaSb layers: morphological evolution and native defects

Undoped and Te-doped gallium antimonide (GaSb) layers have been grown on GaSb bulk substrates by the liquid phase epitaxial technique from Ga-rich and Sb-rich melts. The nucleation morphology of the grown layers has been studied as a function of growth temperature and substrate orientation. MOS structures have been fabricated on the epilayers to evaluate the native defect content in the grown layers from the C-V characteristics. Layers grown from antimony rich melts always exhibit p-type conductivity. In contrast, a type conversion from p- to n- was observed in layers grown from gallium rich melts below 400 degrees C. The electron mobility of undoped n-type layers grown from Ga-rich melts and tellurium doped layers grown from Sb- and Ga-rich solutions has been evaluated.

Effect of post-deposition annealing on composition and electrical properties of dc reactive magnetron sputtered Al2O3 thin films

We have investigated the effect of post- deposition annealing on the composition and electrical properties of alumina (Al2O3) thin films. Al2O3 were deposited on n-type Si < 100 >. substrates by dc reactive magnetron sputtering. The films were subjected to post- deposition annealing at 623, 823 and 1023 K in vacuum. X-ray photoelectron spectroscopy results revealed that the composition improved with post- deposition annealing, and the film annealed at 1023 K became stoichiometric with an O/Al atomic ratio of 1.49. Al/Al2O3/Si metal-oxide-semiconductor (MOS) structures were then fabricated, and a correlation between the dielectric constant epsilon(r) and interface charge density Q(i) with annealing conditions were studied. The dielectric constant of the Al2O3 thin films increased to 9.8 with post- deposition annealing matching the bulk value, whereas the oxide charge density decreased to 3.11 x 10(11) cm(-2.) Studies on current-voltage IV characteristics indicated ohmic and Schottky type of conduction at lower electric fields (<0.16 MV cm(-1)) and space charge limited conduction at higher electric fields.

Low temperature solution processed high-kappa ZrO2 gate dielectrics for nanoelectonics

The high-kappa gate dielectrics, specifically amorphous films offer salient features such as exceptional mechanical flexibility, smooth surfaces and better uniformity associated with low leakage current density. In this work, similar to 35 nm thick amorphous ZrO2 films were deposited on silicon substrate at low temperature (300 degrees C, 1 h) from facile spin-coating method and characterized by various analytical techniques. The X-ray diffraction and X-ray photoelectron spectroscopy reveal the formation of amorphous phase ZrO2, while ellipsometry analysis together with the Atomic Force Microscope suggest the formation of dense film with surface roughness of 1.5 angstrom, respectively. The fabricated films were integrated in metal-oxide-semiconductor (MOS) structures to check the electrical capabilities. The oxide capacitance (C-ox), flat band capacitance (C-FB), flat band voltage (V-FB), dielectric constant (kappa) and oxide trapped charges (Q(ot)) extracted from high frequency (1 MHz) C-V curve are 186 pF, 104 pF, 0.37V, 15 and 2 x 10(-11) C, respectively. The small flat band voltage 0.37V, narrow hysteresis and very little frequency dispersion between 10 kHz-1 MHz suggest an excellent a-ZrO2/Si interface with very less trapped charges in the oxide. The films exhibit a low leakage current density 4.7 x 10(-9)A/cm(2) at 1V. In addition, the charge transport mechanism across the MOSC is analyzed and found to have a strong bias dependence. The space charge limited conduction mechanism is dominant in the high electric field region (1.3-5 V) due to the presence of traps, while the trap-supported tunneling is prevailed in the intermediate region (0.35-1.3 V). Low temperature solution processed ZrO2 thin films obtained are of high quality and find their importance as a potential dielectric layer on Si and polymer based flexible electronics. (C) 2016 Published by Elsevier B.V.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

Pt/anodized TiO2/SiC-based MOS device for hydrocarbon sensing

Pt/anodized TiO2/SiC based metal-oxide-semiconductor (MOS) devices were fabricated and characterized for their sensitivity towards propene (C3H6). Titanium (Ti) thin films were deposited onto the SiC substrates using a filtered cathodic vacuum arc (FCVA) method. Fluoride ions containing neutral electrolyte (0.5 wt% NH4F in ethylene glycol)were used to anodize the Ti films. The anodized films were subsequently annealed at 600 °C for 4 hrs in an oxygen rich environment to obtain TiO2. The current-voltage(I-V) characteristics of the Pt/TiO2/SiC devices were measured in different concentrations of propene. Exposure to the analyte gas caused a change in the Schottky barrier height and hence a lateral shift in the I-V characteristics. The effective change in the barrier height for 1% propene was calculated as 32.8 meV at 620°C. The dynamic response of the sensors was also investigated and a voltage shift of 157 mV was measured at 620°C during exposure to 1% propene.