Número de Milnor associado a curvas reduzidas

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Obstacle Crossing With Dual Tasking Is A Danger For Individuals With Alzheimer's Disease And For Healthy Older People.

The aim of this study was to analyze the effects of dual tasking on obstacle crossing during walking by individuals with Alzheimer's disease (AD) and by healthy older people. Thirty four elderly individuals (16 healthy subjects and 18 individuals with AD) were recruited to participate in this study. Three AD individuals and one control participant were excluded due to exclusion criteria. The participants were instructed to walk barefoot at their own speed along an 8 m long pathway. Each participant performed five trials for each condition (unobstructed walking, unobstructed walking with dual tasking, and obstacle crossing during walking with dual tasking). The trials were completely randomized for each participant. The mid-pathway stride was measured in the unobstructed walking trials and the stride that occurred during the obstacle avoidance was measured in the trials that involved obstacle crossing. The behavior of the healthy elderly subjects and individuals with AD was similar for obstacle crossing during walking with dual tasking. Both groups used the posture first strategy to prioritize stability and showed decreased attention to executive tasking while walking. Additionally, AD had a strong influence on the modifications that are made by the elderly while walking under different walking conditions.

Morphological analysis of glass, carbon and glass/carbon fiber posts and bonding to self or dual-cured resin luting agents

OBJECTIVE: The aim of this study was to evaluate the morphology of glass (GF), carbon (CF) and glass/carbon (G/CF) fiber posts and their bond strength to self or dual-cured resin luting agents. MATERIAL AND METHODS: Morphological analysis of each post type was conducted under scanning electron microscopy (SEM). Bond strength was evaluated by microtensile test after bisecting the posts and re-bonding the two halves with the luting agents. Data were subjected to two-way ANOVA and Tukey's test (α=0.05). Failure modes were evaluated under optical microscopy and SEM. RESULTS: GF presented wider fibers and higher amount of matrix than CF, and G/CF presented carbon fibers surrounded by glass fibers, and both involved by matrix. For CF and GF, the dual-cured material presented significantly higher (p<0.05) bond strength than the self-cured agent. For the dual agent, CF presented similar bond strength to GF (p>0.05), but higher than that of G/CF (p<0.05). For the self-cured agent, no significant differences (p>0.05) were detected, irrespective of the post type. For GF and G/CF, all failures were considered mixed, while a predominance of adhesive failures was detected for CF. CONCLUSION: The bonding between fiber posts and luting agents was affected by the type of fibers and polymerization mode of the cement. When no surface treatment of the post is performed, the bonding between glass fiber post and dual-cured agent seems to be more reliable.

Bilayer graphene dual-gate nanodevice: An ab initio simulation

We study the electronic transport properties of a dual-gated bilayer graphene nanodevice via first-principles calculations. We investigate the electric current as a function of gate length and temperature. Under the action of an external electrical field we show that even for gate lengths up 100 angstrom, a nonzero current is exhibited. The results can be explained by the presence of a tunneling regime due the remanescent states in the gap. We also discuss the conditions to reach the charge neutrality point in a system free of defects and extrinsic carrier doping.

Dual contactless conductivity and amperometric detection on hybrid PDMS/glass electrophoresis microchips

A new approach for the integration of dual contactless conductivity and amperometric detection with an electrophoresis microchip system is presented. The PDMS layer with the embedded channels was reversibly sealed to a thin glass substrate (400 mu m), on top of which a palladium electrode had been previously fabricated enabling end-channel amperometric detection. The thin glass substrate served also as a physical wall between the separation channel and the sensing copper electrodes for contactless conductivity detection. The latter were not integrated in the microfluidic device, but fabricated on an independent plastic substrate allowing a simpler and more cost-effective fabrication of the chip. PDMS/glass chips with merely contactless conductivity detection were first characterized in terms of sensitivity, efficiency and reproducibility. The separation efficiency of this system was found to be similar or slightly superior to other systems reported in the literature. The simultaneous determination of ionic and electroactive species was illustrated by the separation of peroxynitrite degradation products, i.e. NO(3)(-) (non-electroactive) and NO(2)(-) (electroactive), using hybrid PDMS/glass chips with dual contactless conductivity and amperometric detection. While both ions were detected by contactless conductivity detection with good efficiency, NO(2)(-) was also simultaneously detected amperometrically with a significant enhancement in sensitivity compared to contactless conductivity detection.

Dual-task interference: Attentional and neurophysiological influences

Performing two tasks simultaneously often degrades performance of one or both tasks. While this dual-task interference is classically interpreted in terms of shared attentional resources, where two motor tasks are performed simultaneously interactions within primary motor cortex (i.e., activity-dependent coupling) may also be a contributing factor. In the present study TMS (transcranial magnetic stimulation) was used to examine the contribution of activity-dependent coupling to dual-task interference during concurrent performance of a bimanual coordination task and a discrete probe reaction time (RT) task involving the foot. Experiments 1 and 2 revealed that activity-dependent coupling within the leg corticomotor pathway was greater during dual-task performance than single-task performance, and this was associated with interference on the probe RT task (i.e., increased RT). Experiment 3 revealed that dual-task interference occurred regardless of whether the dual-task involved two motor tasks or a motor and cognitive task, however activity-dependent coupling was present only when a dual motor task was performed. This suggests that activity-dependent coupling is less detrimental to performance than attentional processes operating upstream of the corticomotor system. Finally, while prioritising the RT task reduced, but did not eliminate, dual-task interference the contribution of activity-dependent coupling to dual-task interference was not affected by task prioritisation. This suggests that although activity-dependent coupling may contribute to dual motor-task interference, attentional processes appear to be more important. It also suggests that activity-dependent coupling may not be subject to modulation by attentional processes. (C) 2009 Elsevier B.V. All rights reserved.

Dual boundary element formulation applied to analysis of multi-fractured domains

This paper deals with analysis of multiple random crack propagation in two-dimensional domains using the boundary element method (BEM). BEM is known to be a robust and accurate numerical technique for analysing this type of problem. The formulation adopted in this work is based on the dual BEM, for which singular and hyper-singular integral equations are used. We propose an iterative scheme to predict the crack growth path and the crack length increment at each time step. The proposed scheme able us to simulate localisation and coalescence phenomena, which is the main contribution of this paper. Considering the fracture mechanics analysis, the displacement correlation technique is applied to evaluate the stress intensity factors. The propagation angle and the equivalent stress intensity factor are calculated using the theory of maximum circumferential stress. Examples of simple and multi-fractured domains, loaded up to the rupture, are considered to illustrate the applicability of the proposed scheme. (C) 2010 Elsevier Ltd. All rights reserved.

Performance evaluation of dual-flush WC cistern in a multifamily building in Brazil

The performance assessment as to water consumption in WC cisterns has contributed to the development of flushing system technologies, which allow smaller flushing volumes. The purpose of this work is to assess the performance of the the low water consumption requirement of WC cisterns with dual flushing system (6/3L), when compared to 6L flushing volume WC cisterns in multifamily buildings. The research methodology consisted of a case study in a multifamily residential building with submetering system, by monitoring the total water consumption and the two flushing systems using water meters installed in WC cisterns. By means of a mathematical model, a comparison of the design flowrate in the main branch was carried out considering the two types of WC cisterns. The results indicated that the water consumption in the 6L WC cistern was 20% in relation to the total domestic consumption, whereas the water consumption observed in the dual-flush WC cistern (6/3L) was 16%. The dual flushing system (6/3L) presented about 18% consumption reduction impact as compared to the 6 L system. The design flowrate values in the main branch, obtained by the mathematical model, were 0.35 L/s for systems with 6 L WC cistern and 0.34 L/s with dual-flush WC cistern (6/3 L), that is, a reduction of similar to 3%. Practical application: The knowledge of the performance in field of dual-flush WC cistern contributes to industry to improve this system and to users to aid their choice of technologies aimed at water conservation, and so assisting to the development of sustainable buildings.

Conservation of dual-targeted proteins in Arabidopsis and rice points to a similar pattern of gene-family evolution

Gene duplication followed by acquisition of specific targeting information and dual targeting were evolutionary strategies enabling organelles to cope with overlapping functions. We examined the evolutionary trend of dual-targeted single-gene products in Arabidopsis and rice genomes. The number of paralogous proteins encoded by gene families and the dual-targeted orthologous proteins were analysed. The number of dual-targeted proteins and the corresponding gene-family sizes were similar in Arabidopsis and rice irrespective of genome sizes. We show that dual targeting of methionine aminopeptidase, monodehydroascorbate reductase, glutamyl-tRNA synthetase, and tyrosyl-tRNA synthetase was maintained despite occurrence of whole-genome duplications in Arabidopsis and rice as well as a polyploidization followed by a diploidization event (gene loss) in the latter.

Morphine has a dual concentration-dependent effect on K+-evoked substance P release from rat peripheral airways

Our previous investigations of possible lung mechanisms underlying the effectiveness of nebulized morphine for the relief of dyspnoea, have shown a high density of non-conventional opioid binding sites in rat airways with similar binding characteristics (opioid alkaloid-sensitive, opioid peptide-insensitive) to that of putative mu(3)-opioid receptors on immune cells. To investigate whether these lung opioid binding sites are functional receptors, this study was designed to determine (using superfusion) whether morphine modulates the K+-evoked release of the pro-inflammatory neuropeptide, substance P (SP), from rat peripheral airways. Importantly, K+-evoked SP release was Ca2+-dependent, consistent with vesicular release. Submicromolar concentrations of morphine (1 and 200 nM) inhibited K+-evoked SP release from rat peripheral airways in a naloxone (1 mu M) reversible manner. By contrast, 1 mu M morphine enhanced K+-evoked SP release and this effect was not reversed by 1 mu M naloxone. However, 100 mu M naloxone not only antagonized the facilitatory effect of 1 mu M morphine on K+-evoked SP release from rat peripheral airways but it inhibited release to a similar extent as 200 nM morphine. It is possible that these latter effects are mediated by non-conventional opioid receptors located on mast cells, activation of which causes naloxone-reversible histamine release that in turn augments the release of SP from sensory nerve terminals in the peripheral airways. Clearly, further studies are required to investigate this possibility. (C) 1997 Academic Press Limited.

Asymptotic limits of a self-dual Ginzburg-Landau functional in bounded domains

In the author's joint paper [HJS] with Jest and Struwe, we discuss asymtotic limits of a self-dual Ginzburg-Landau functional involving a section of a line bundle over a closed Riemann surface and a connection on this bundle. In this paper, the author generalizes the above results [HJS] to the case of bounded domains.

Assessment of limb muscle and adipose tissue by dual-energy X-ray absorptiometry using magnetic resonance imaging for comparison

OBJECTIVE: To use magnetic resonance imaging (MRI) to validate estimates of muscle and adipose tissue (AT) in lower limb sections obtained by dual-energy X-ray absorptiometry (DXA) modelling. DESIGN: MRI measurements were used as reference for validating limb muscle and AT estimates obtained by DXA models that assume fat-free soft tissue (FFST) comprised mainly muscle: model A accounted for bone hydration only; model B also applied constants for FFST in bone and skin and fat in muscle and AT; model C was as model B but allowing for variable fat in muscle and AT. SUBJECTS: Healthy men (n = 8) and women (n = 8), ages 41 - 62 y; mean (s.d.) body mass indices (BMIs) of 28.6 (5.4) kg/m(2) and 25.1 (5.4) kg/m2, respectively. MEASUREMENTS: MRI scans of the legs and whole body DXA scans were analysed for muscle and AT content of thigh (20 cm) and lower leg (10 cm) sections; 24 h creatinine excretion was measured. RESULTS: Model A overestimated thigh muscle volume (MRI mean, 2.3 l) substantially (bias 0.36 l), whereas model B underestimated it by only 2% (bias 0.045 l). Lower leg muscle (MRI mean, 0.6 l) was better predicted using model A (bias 0.04 l, 7% overestimate) than model B (bias 0.1 l, 17% underestimate). The 95% limits of agreement were high for these models (thigh,+/- 20%; lower leg,+/- 47%). Model C predictions were more discrepant than those of model B. There was generally less agreement between MRI and all DXA models for AT. Measurement variability was generally less for DXA measurements of FFST (coefficient of variation 0.7 - 1.8%) and fat (0.8 - 3.3%) than model B estimates of muscle (0.5-2.6%) and AT (3.3 - 6.8%), respectively. Despite strong relationships between them, muscle mass was overestimated by creatinine excretion with highly variable predictability. CONCLUSION: This study has shown the value of DXA models for assessment of muscle and AT in leg sections, but suggests the need to re-evaluate some of the assumptions upon which they are based.

Dual processes in recognition: Does a focus on measurement operations provide a sufficient foundation?

Current theoretical thinking about dual processes in recognition relies heavily on the measurement operations embodied within the process dissociation procedure. We critically evaluate the ability of this procedure to support this theoretical enterprise. We show that there are alternative processes that would produce a rough invariance in familiarity (a key prediction of the dual-processing approach) and that the process dissociation procedure does not have the power to differentiate between these alternative possibilities. We also show that attempts to relate parameters estimated by the process dissociation procedure to subjective reports (remember-know judgments) cannot differentiate between alternative dual-processing models and that there are problems with some of the historical evidence and with obtaining converging evidence. Our conclusion is that more specific theories incorporating ideas about representation and process are required.

A dual catalyst bed system for the elimination of hydrogen from CO2 feed gas in urea synthesis

A dual catalyst bed system (Au/Fe2O3 + Pt-Pd/Al2O3) for eliminating hydrogen from the CO2 feed gas in urea synthesis is found to be far superior to commercially available and patented catalysts in catalytic activity. At relatively low temperatures, hydrogen is eliminated and coexistent CO is also oxidized completely to useful CO2. This can avoid effectively the accidental explosion of hydrogen-oxygen-ammonia mixed gases, thus ensuring the safety of urea synthesis.