Development and efficiency optimizing of the human body energy converters

Nowadays it is known that the human body is continuous source of many types of energy and the devices used for collecting energy taken from the environment also have the required capabilities for the collection of the energy produced by the Human body (HB), but very limited and with very low efficiency. Low power and high yield converters are particularly needed in these cases of collecting energy from human activity and its movements due to the small amount of energy generated this way. But this situation can be improved. Enhancing or focusing the human movements by using mechanical amplifiers applied to the piezoelectric element. By doing so the input of energy in the element increases. As such increasing its output, therefore producing more energy.

A low-voltage low-power analog memory cell with built-in 4-quadrant multiplication

An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is provided. A simplified 2 x 2-memory array was prototyped according to a standard 0.8 mum n-well CMOS process and 1.8-V supply. Measured current-reproduction error is less than 0.26% for 0.25 muA less than or equal to I-SAMPLE less than or equal to 0.75 muA. Standby consumption is 6.75 muW per cell @I-SAMPLE = 0.75 muA. At room temperature, leakage-rate is 1.56 nA/ms. Four-quadrant multiplier (4QM) full-scale operands are 2x(max) = 320 mV(pp) and 2y(max). = 448 mV(pp), yielding a maximum output swing of 0.9 muA(pp). 4QM worst-case nonlinearity is 7.9%.

A Gm-C bump equalizer for low-voltage low-power applications

A low-voltage low-power 2nd-order CMOS pseudo-differential bump-equalizer is presented. Its topology comprises a bandpass section with adjustable center frequency and quality factor, together with a programmable current amplifier. The basic building blocks are triode-operating transconductors, tunable by means of either a DC voltage or a digitally controlled current divider. The bump-equalizer as part of a battery-operated hearing aid device is designed for a 1.4V-supply and a 0.35μm CMOS fabrication process. The circuit performance is supported by a set of simulation results, which indicates a center frequency from 600Hz to 2.4kHz, 1≤Q≤5, and an adjustable gain within ±6dB at center frequency. The filter dynamic range lies around 40dB. Quiescent consumption is kept below 12μW for any configuration of the filter.

Start-up circuit for low-power indoor light energy harvesting applications

A start-up circuit, used in a micro-power indoor light energy harvesting system, is described. This start-up circuit achieves two goals: first, to produce a reset signal, power-on-reset (POR), for the energy harvesting system, and secondly, to temporarily shunt the output of the photovoltaic (PV) cells, to the output node of the system, which is connected to a capacitor. This capacitor is charged to a suitable value, so that a voltage step-up converter starts operating, thus increasing the output voltage to a larger value than the one provided by the PV cells. A prototype of the circuit was manufactured in a 130 nm CMOS technology, occupying an area of only 0.019 mm(2). Experimental results demonstrate the correct operation of the circuit, being able to correctly start-up the system, even when having an input as low as 390 mV using, in this case, an estimated energy of only 5.3 pJ to produce the start-up.

A 5GHz1.8V Low Power CMOS Low-Noise Amplifier

Wireless local-area networks (WLANs) have been deployed as office and home communications infrastructures worldwide. The diversification of the standards, such as IEEE 802.11 series demands the design of RF front-ends. Low power consumption is one of the most important design concerns in the application of those technologies. To maintain competitive hardware costs, CMOS has been used since it is the best solution for low cost and high integration processing, allowing analog circuits to be mixed with digital ones. In the receiver chain, the low noise amplifier (LNA) is one of the most critical blocks in a transceiver design. The sensitivity is mainly determined by the LNA noise figure and gain. It interfaces with the pre-select filter and the mixer. Furthermore, since it is the first gain stage, care must be taken to provide accurate input match, low-noise figure, good linearity and a sufficient gain over a wide band of operation. Several CMOS LNAs have been reported during the last decade, showing that the most research has been done at 802.11/b and GSM standards (900-2400MHz spectrum) and more recently at 802.11/a (5GHz band). One of the more significant disadvantages of 802.11/b is that the frequency band is crowded and subject to interference from other technologies, as is 2.4GHz cordless phones and Bluetooth. As the demand for radio-frequency integrated circuits, operating at higher frequency bands, increases, the IEEE 802.11/a standard becomes a very attractive option to wireless communication system developers. This paper presents the design and implementation of a low power, low noise amplifier aimed at IEEE 802.11a for WLAN applications. It was designed to be integrated with an active balun and mixer, representing the first step toward a fully integrated monolithic WLAN receiver. All the required circuits are integrated at the same die and are powered by 1.8V supply source. Preliminary experimental results (S-parameters) are shown and promise excellent results. The LNA circuit design details are illustrated in Section 2. Spectre simulation results focused at gain, noise figure (NF) and input/output matching are presented in Section 3. Finally, conclusions and comparison with other recently reported LNAs are made in Section 4, followed by future work.

Low-voltage low-power CMOS analogue circuits for Gaussian and uniform noise generation

IEEE International Symposium on Circuits and Systems, MAY 25-28, 2003, Bangkok, Thailand. (ISI Web of Science)

New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification

15th IEEE International Conference on Electronics, Circuits and Systems, Malta

Low power low voltage quadrature RC oscillators for modern RF receivers

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores

Spectral efficiency in reference-signal-assisted low-power wireless communication

Expressions relating spectral efficiency, power and Doppler spectrum are derived for low-power Rayleighfaded wireless channels with proper complex signaling. Noside information on the state of the channel is assumed at the receiver. Rather, periodic reference signals are postulated inaccordance with the functioning of most wireless systems. In contrast with most previous studies, which relied on block-fading channel models, a continuous-fading model is adopted. This embeds the Doppler spectrum directly in thederived expressions thereby imbuing them with practical significance.

Improving the efficiency of PV low-power processing circuits by selecting an optimal inductor current of the DC/DC converter

In the context of autonomous sensors powered by small-size photovoltaic (PV) panels, this work analyses how the efficiency of DC/DC-converter-based power processing circuits can be improved by an appropriate selection of the inductor current that transfers the energy from the PV panel to a storage unit. Each component of power losses (fixed, conduction and switching losses) involved in the DC/DC converter specifically depends on the average inductor current so that there is an optimal value of this current that causes minimal losses and, hence, maximum efficiency. Such an idea has been tested experimentally using two commercial DC/DC converters whose average inductor current is adjustable. Experimental results show that the efficiency can be improved up to 12% by selecting an optimal value of that current, which is around 300-350 mA for such DC/DC converters.

Investigation into low power of a 2D Inverse Discrete CosineTransform (IDCT) in FPGAs

Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level(1).

An efficient low power FFT implementation for multiband full-rate ultra-wideband (UWB) receivers

This paper discusses the design, implementation and synthesis of an FFT module that has been specifically optimized for use in the OFDM based Multiband UWB system, although the work is generally applicable to many other OFDM based receiver systems. Previous work has detailed the requirements for the receiver FFT module within the Multiband UWB ODFM based system and this paper draws on those requirements coupled with modern digital architecture principles and low power design criteria to converge on our optimized solution. The FFT design obtained in this paper is also applicable for implementation of the transmitter IFFT module therefore only needing one FFT module for half-duplex operation. The results from this paper enable the baseband designers of the 200Mbit/sec variant of Multiband UWB systems (and indeed other OFDM based receivers) using System-on-Chip (SoC), FPGA and ASIC technology to create cost effective and low power solutions biased toward the competitive consumer electronics market.

Single stage converters for low power stand-alone and grid-connected PV systems

This work presents the evaluation of different power electronic integrated converters suitable for photovoltaic applications, in order to reduce complexity and improve reliability. The rated voltages available in Photovoltaic (PV) modules have usually low values for applications such as regulated output voltages in stand-alone or grid-connected configurations. In these cases, a boost stage or a transformer will be necessary. Transformers have low efficiencies, heavy weights and have been used only when galvanic isolation is mandatory. Furthermore, high-frequency transformers increase the converter complexity. Therefore, the most usual topologies use a boost stage and one inverter stage cascaded. However, the complexity, size, weight, cost and lifetime might be improved considering the integration of both stages. In this context, some integrated converters are analyzed and compared in this paper in order to support future evaluations and trends for low power single-phase inverters for PV systems. Power decoupling, MPPT and Tri-State modulations are also considered. Finally, simulation and experimental results are presented and compared for the analyzed topologies. © 2011 IEEE.

Evaluation of integrated inverter topologies for low power PV systems

This work presents the stage integration in power electronics converters as a suitable solution for solar photovoltaic inverters. The rated voltages available in Photovoltaic (PV) modules have usually low values for applications such as regulated output voltages in stand-alone or grid-connected configurations. In these cases, a boost stage or a transformer will be necessary. Transformers have low efficiencies, heavy weights and have been used only when galvanic isolation is mandatory. Furthermore, high-frequency transformers increase the converter complexity. Therefore, the most usual topologies use a boost stage and one inverter stage cascaded. However, the complexity, size, weight, cost and lifetime might be improved considering the integration of both stages. These are the expected features to turn attractive this kind of integrated structures. Therefore, some integrated converters are analyzed and compared in this paper in order to support future evaluations and trends for low power single-phase inverters for PV systems. © 2011 IEEE.

A low-power silicon-on-insulator PWM discriminator for biomedical applications

A CMOS/SOI circuit to decode PWM signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a double-integration concept and does not require dc filtering. Nonoverlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 mu m single-metal SOI fabrication process and has an effective area of 2mm(2) Typically, the measured resolution of encoding parameter a was better than 10% at 6MHz and V-DD=3.3V. Stand-by consumption is around 340 mu W. Pulses with frequencies up to 15MHz and alpha = 10% can be discriminated for V-DD spanning from 2.3V to 3.3V. Such an excellent immunity to V-DD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.