867 resultados para Loop delay estimator


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Most adaptive linearization circuits for the nonlinear amplifier have a feedback loop that returns the output signal oj'tne eunplifier to the lineurizer. The loop delay of the linearizer most be controlled precisely so that the convergence of the linearizer should be assured lot this Letter a delay control circuit is presented. It is a delay lock loop (ULL) with it modified early-lute gate and can he easily applied to a DSP implementation. The proposed DLL circuit is applied to an adaptive linearizer with the use of a polynomial predistorter, and the simulalion for a 16-QAM signal is performed. The simulation results show that the proposed DLL eliminates the delay between the reference input signal and the delayed feedback signal of the linearizing circuit perfectly, so that the predistorter polynomial coefficients converge into the optimum value and a high degree of linearization is achieved

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This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.

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Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e Computadores

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A theoretical and experimental investigation of the time delay characteristics of fiber Bragg grating-based Sagnac loops (FBGSLs) is presented. Analytic expressions for the phase and time delay of the FBGSL have been derived and excellent agreement is found between their predictions and experimental results for configurations incorporating uniform-period and chirped-period gratings. For symmetrical grating structures, it is found that the FBGSL time delay response is similar to that of the incorporated grating; with asymmetrical gratings, the FBGSL response is quite different. It is shown that wavelength-division-multiplexing filters exhibiting near-zero dispersion characteristics can be implemented using FBGSLs.

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We have developed the analytic expressions for the phase response and time delay of FBGSL of arbitrary grating structure and found that the results from the modelling are in excellent agreement with that of the experimentally measured real devices. The theoretical and experimental investigation clearly reveals that FBGSLs utilizing uniform and linearly chirped gratings exhibit a near-constant time delay in the passbands. Such multi-channel bandpass filters should be highly attractive to WDM applications as they are operating in transmission regime and offering near-zero dispersion.

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Considering the increasing popularity of network-based control systems and the huge adoption of IP networks (such as the Internet), this paper studies the influence of network quality of service (QoS) parameters over quality of control parameters. An example of a control loop is implemented using two LonWorks networks (CEA-709.1) interconnected by an emulated IP network, in which important QoS parameters such as delay and delay jitter can be completely controlled. Mathematical definitions are provided according to the literature, and the results of the network-based control loop experiment are presented and discussed.

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We investigate the problem of finding minimum-distortion policies for streaming delay-sensitive but distortion-tolerant data. We consider cross-layer approaches which exploit the coupling between presentation and transport layers. We make the natural assumption that the distortion function is convex and decreasing. We focus on a single source-destination pair and analytically find the optimum transmission policy when the transmission is done over an error-free channel. This optimum policy turns out to be independent of the exact form of the convex and decreasing distortion function. Then, for a packet-erasure channel, we analytically find the optimum open-loop transmission policy, which is also independent of the form of the convex distortion function. We then find computationally efficient closed-loop heuristic policies and show, through numerical evaluation, that they outperform the open-loop policy and have near optimal performance.

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This paper addresses the estimation of the code-phase(pseudorange) and the carrier-phase of the direct signal received from a direct-sequence spread-spectrum satellite transmitter. Thesignal is received by an antenna array in a scenario with interferenceand multipath propagation. These two effects are generallythe limiting error sources in most high-precision positioning applications.A new estimator of the code- and carrier-phases is derivedby using a simplified signal model and the maximum likelihood(ML) principle. The simplified model consists essentially ofgathering all signals, except for the direct one, in a component withunknown spatial correlation. The estimator exploits the knowledgeof the direction-of-arrival of the direct signal and is much simplerthan other estimators derived under more detailed signal models.Moreover, we present an iterative algorithm, that is adequate for apractical implementation and explores an interesting link betweenthe ML estimator and a hybrid beamformer. The mean squarederror and bias of the new estimator are computed for a numberof scenarios and compared with those of other methods. The presentedestimator and the hybrid beamforming outperform the existingtechniques of comparable complexity and attains, in manysituations, the Cramér–Rao lower bound of the problem at hand.

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The present study examined the effects of a pre-movement delay on the kinematics of prehension in middle childhood. Twenty-five children between the ages of 5 and 11 years made visually open-loop reaches to two different sized objects at two different distances along the midline. Reaches took place either (i) immediately, or (ii) 2 s after the occlusion of the stimulus. In all age groups, reaches following the pre-movement delay were characterised by longer movement durations, lower peak velocities, larger peak grip apertures and longer time spent in the final slow phase of the movement. This pattern of results suggests that the representations that control the transport and grasp component are affected similarly by delay, and is consistent with the results previously reported for adults. Such representations therefore appear to develop before the age of 5. (C) 2004 Elsevier B.V. All rights reserved.

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This correspondence introduces a new orthogonal forward regression (OFR) model identification algorithm using D-optimality for model structure selection and is based on an M-estimators of parameter estimates. M-estimator is a classical robust parameter estimation technique to tackle bad data conditions such as outliers. Computationally, The M-estimator can be derived using an iterative reweighted least squares (IRLS) algorithm. D-optimality is a model structure robustness criterion in experimental design to tackle ill-conditioning in model Structure. The orthogonal forward regression (OFR), often based on the modified Gram-Schmidt procedure, is an efficient method incorporating structure selection and parameter estimation simultaneously. The basic idea of the proposed approach is to incorporate an IRLS inner loop into the modified Gram-Schmidt procedure. In this manner, the OFR algorithm for parsimonious model structure determination is extended to bad data conditions with improved performance via the derivation of parameter M-estimators with inherent robustness to outliers. Numerical examples are included to demonstrate the effectiveness of the proposed algorithm.

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In this paper we use the Hermite-Biehler theorem to establish results for the design of fixed order controllers for a class of time delay systems. We extend results of the polynomial case to quasipolynomials using the property of interlacing in high frequencies of the class of time delay systems considered. (C) 2003 Elsevier B.V. All rights reserved.

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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

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Model predictive control (MPC) applications in the process industry usually deal with process systems that show time delays (dead times) between the system inputs and outputs. Also, in many industrial applications of MPC, integrating outputs resulting from liquid level control or recycle streams need to be considered as controlled outputs. Conventional MPC packages can be applied to time-delay systems but stability of the closed loop system will depend on the tuning parameters of the controller and cannot be guaranteed even in the nominal case. In this work, a state space model based on the analytical step response model is extended to the case of integrating time systems with time delays. This model is applied to the development of two versions of a nominally stable MPC, which is designed to the practical scenario in which one has targets for some of the inputs and/or outputs that may be unreachable and zone control (or interval tracking) for the remaining outputs. The controller is tested through simulation of a multivariable industrial reactor system. (C) 2012 Elsevier Ltd. All rights reserved.

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This work proposes the development of an Adaptive Neuro-fuzzy Inference System (ANFIS) estimator applied to speed control in a three-phase induction motor sensorless drive. Usually, ANFIS is used to replace the traditional PI controller in induction motor drives. The evaluation of the estimation capability of the ANFIS in a sensorless drive is one of the contributions of this work. The ANFIS speed estimator is validated in a magnetizing flux oriented control scheme, consisting in one more contribution. As an open-loop estimator, it is applied to moderate performance drives and it is not the proposal of this work to solve the low and zero speed estimation problems. Simulations to evaluate the performance of the estimator considering the vector drive system were done from the Matlab/Simulink(R) software. To determine the benefits of the proposed model, a practical system was implemented using a voltage source inverter (VSI) to drive the motor and the vector control including the ANFIS estimator, which is carried out by the Real Time Toolbox from Matlab/Simulink(R) software and a data acquisition card from National Instruments.

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The endogenous clock that drives circadian rhythms is thought to communicate temporal information within the cell via cycling downstream transcripts. A transcript encoding a glycine-rich RNA-binding protein, Atgrp7, in Arabidopsis thaliana undergoes circadian oscillations with peak levels in the evening. The AtGRP7 protein also cycles with a time delay so that Atgrp7 transcript levels decline when the AtGRP7 protein accumulates to high levels. After AtGRP7 protein concentration has fallen to trough levels, Atgrp7 transcript starts to reaccumulate. Overexpression of AtGRP7 in transgenic Arabidopsis plants severely depresses cycling of the endogenous Atgrp7 transcript. These data establish both transcript and protein as components of a negative feedback circuit capable of generating a stable oscillation. AtGRP7 overexpression also depresses the oscillation of the circadian-regulated transcript encoding the related RNA-binding protein AtGRP8 but does not affect the oscillation of transcripts such as cab or catalase mRNAs. We propose that the AtGRP7 autoregulatory loop represents a “slave” oscillator in Arabidopsis that receives temporal information from a central “master” oscillator, conserves the rhythmicity by negative feedback, and transduces it to the output pathway by regulating a subset of clock-controlled transcripts.