The LDC debt problem: a game-theoretical analisys

We review the LDC debt crisis since 1982, by means of game theory. New insights are obtained into the reasons behind the formation of the creditors' carte1 and the nature of the difficu1ties invo1ved in the formation of the debtors' carte1. The standard view that Rubinstein's barganing mode1s are appropriate for dea1ing with debt re1ief is shown to be faulty, un1ess the debtor buys out the debt.

Water supply situation in the LDC's of the East Caribbean at the beginning of the International Drinking Water Supply and Sanitation Decade: a brief note

Includes bibliography

A strategy paper for integrating LDC rural women into their national economies /

At head of title: Prepared for the AID Percy Amendment Subcommittee on Agriculture, Nutrition and Rural Development.

Trends in LDC external debt /

Description based on: 1983-89.

Non-OPEC LDC terms of trade, 1970-77 : a research paper /

"ER 79-10145."

Meta-regulation approach of law : a potential legal strategy to develop socially responsible business self-regulation in least developed common law countries

In the corporate regulation landscape, 'meta-regulation' is a comparatively new legal approach. The sketchy role of state promulgated authoritative laws in pluralized society and scepticism in corporate self-regulation's role have resulted in the development of this legal approach. It has opened up possibilities to synthesize corporate governance to add social values in corporate self-regulation. The core of this approach is the fusion of responsive and reflexive legal strategies to combine regulators and regulatees for reaching a particular goal. This paper argues that it is a potential strategy that can be successfully deployed to develop a socially responsible corporate culture for the business enterprises, so that they will be able to acquire social, environmental and ethical values in their self-regulation sustainably. Taking Bangladeshi corporate laws as an instance, this paper also evaluates the scope of incorporating this approach in laws of the least developed common law countries in general.

A coordinated voltage control approach for coordination of OLTC, voltage regulator and DG to regulate voltage in a distribution feeder

Integration of small-scale electricity generators, known as Distributed Generation (DG), into the distribution networks has become increasingly popular at the present. This tendency together with the falling price of synchronous-type generator has potential to give the DG a better chance in participating in the voltage regulation process together with other devices already available in the system. The voltage control issue turns out to be a very challenging problem for the distribution engineers since existing control coordination schemes would need to be reconsidered to take into account the DG operation. In this paper, we propose a control coordination technique, which is able to utilize the ability of the DG as a voltage regulator, and at the same time minimizes interaction with other active devices, such as On-load Tap Changing Transformer (OLTC) and voltage regulator. The technique has been developed based on the concept of control zone, Line Drop Compensation (LDC), as well as the choice of controller's parameters. Simulations carried out on an Australian system show that the technique is suitable and flexible for any system with multiple regulating devices including DG.

Temperature dependence of the dielectric constant of diamond

The temperature dependence of the dielectric constant of diamond has been measured over the temperature range 50-2OO"c. The value of E-ldc dT over this range is + 1 x 10-j. Details of the method of measuring the temperature coefficient of dielectric constant are also given. The magnitude and sign of c-ldc, dT for diamond has been theoretically calculated using Maxwell's relationship and Kramers-Heisenberg theory. The agreement between theoretical and experimental values is extremely good.

Non-unitary-weight Space-Time Block Codes with Minimum Decoding Complexity

Space-Time Block Codes (STBCs) from Complex Orthogonal Designs (CODs) are single-symbol decodable/symbol-by-symbol decodable (SSD); however, SSD codes are obtainable from designs that are not CODs. Recently, two such classes of SSD codes have been studied: (i) Coordinate Interleaved Orthogonal Designs (CIODs) and (ii) Minimum-Decoding-Complexity (MDC) STBCs from Quasi-ODs (QODs). The class of CIODs have non-unitary weight matrices when written as a Linear Dispersion Code (LDC) proposed by Hassibi and Hochwald, whereas the other class of SSD codes including CODs have unitary weight matrices. In this paper, we construct a large class of SSD codes with nonunitary weight matrices. Also, we show that the class of CIODs is a special class of our construction.

Analyzing Cache Performance Bottlenecks of STM Applications and addressing them with Compiler's help

Software transactional memory (STM) is a promising programming paradigm for shared memory multithreaded programs as an alternative to traditional lock based synchronization. However adoption of STM in mainstream software has been quite low due to its considerable overheads and its poor cache/memory performance. In this paper, we perform a detailed study of the cache behavior of STM applications and quantify the impact of different STM factors on the cache misses experienced by the applications. Based on our analysis, we propose a compiler driven Lock-Data Colocation (LDC), targeted at reducing the cache overheads on STM. We show that LDC is effective in improving the cache behavior of STM applications by reducing the dcache miss latency and improving execution time performance.

Making STMs Cache Friendly with Compiler Transformations

Software transactional memory (STM) is a promising programming paradigm for shared memory multithreaded programs. In order for STMs to be adopted widely for performance critical software, understanding and improving the cache performance of applications running on STM becomes increasingly crucial, as the performance gap between processor and memory continues to grow. In this paper, we present the most detailed experimental evaluation to date, of the cache behavior of STM applications and quantify the impact of the different STM factors on the cache misses experienced by the applications. We find that STMs are not cache friendly, with the data cache stall cycles contributing to more than 50% of the execution cycles in a majority of the benchmarks. We find that on an average, misses occurring inside the STM account for 62% of total data cache miss latency cycles experienced by the applications and the cache performance is impacted adversely due to certain inherent characteristics of the STM itself. The above observations motivate us to propose a set of specific compiler transformations targeted at making the STMs cache friendly. We find that STM's fine grained and application unaware locking is a major contributor to its poor cache behavior. Hence we propose selective Lock Data co-location (LDC) and Redundant Lock Access Removal (RLAR) to address the lock access misses. We find that even transactions that are completely disjoint access parallel, suffer from costly coherence misses caused by the centralized global time stamp updates and hence we propose the Selective Per-Partition Time Stamp (SPTS) transformation to address this. We show that our transformations are effective in improving the cache behavior of STM applications by reducing the data cache miss latency by 20.15% to 37.14% and improving execution time by 18.32% to 33.12% in five of the 8 STAMP applications.