Alternative positional FEM applied to thermomechanical impact of truss structures

This paper presents a formulation to deal with dynamic thermomechanical problems by the finite element method. The proposed methodology is based on the minimum potential energy theorem written regarding nodal positions, not displacements, to solve the mechanical problem. The thermal problem is solved by a regular finite element method. Such formulation has the advantage of being simple and accurate. As a solution strategy, it has been used as a natural split of the thermomechanical problem, usually called isothermal split or isothermal staggered algorithm. Usual internal variables and the additive decomposition of the strain tensor have been adopted to model the plastic behavior. Four examples are presented to show the applicability of the technique. The results are compared with other authors` numerical solutions and experimental results. (C) 2010 Elsevier B.V. All rights reserved.

Key factors in working capital management in the Brazilian market

Many studies have been conducted in corporate finance regarding long-term investment and financing decisions. However, short-term asset investments play a significant role in the balance sheet of companies. Moreover, financial managers dedicate significant amounts of time and effort to the subject of working capital management, balancing current assets and liabilities. This paper provides insights regarding the key factors of working capital management by exploring the internal variables of a number of companies. This study used data from 2,976 Brazilian public companies from 2001 to 2008, and found that debt level, size and growth rate can affect the working capital management of companies.

Two divergent ways to manage HR and to get to the top: an exploratory study in micro firms

Aim of the paper: The purpose of this paper is to examine human resources management practices (HRM practices) in small firms and to improve the understanding of the relationship between this kind of practices and business growth. This exploratory study is based on the resource-based view of the firm and empirical work carried out in two small firms by relating HRM practices with the firms’ results. Contribution to the literature: This is an in-depth study of HRM practices and its impact on performance growth in micro firms, isolating and controlling for most of the contextual and internal variables considered in the literature that relate HRM to growth. Firm growth analysis was broadened by the use of several dependent variables: employment growth and operational and financial performance growth. Some hypotheses for further research in identifying HRM practices in small business and its relation with firm growth are suggested. Methodology: Case study methodology was used to study two firms. The techniques used to collect data were semi-structured interviews to the owner and all the employees, unstructured observation at the firms’ facilities (during two days), entrepreneur profile definition (survey answer) and document data collection (on demographic characterization and performance results). Data was analyzed through content analysis methodology, and categories derived from the interviews’ protocols and literature. Results and implications: Results revealed that despite the firms’ organizational characteristics similarities, they differ significantly in owners’ motivation to grow, HRM practices and organizational performance and growth. Future studies should pay special attention to owner willingness to grow, to firms’ years of experience in business, to staff’s years of experience in their field of work and turnover. HRM practices in micro/small firms should be better defined and characterized. The external image of management posture relating to longitudinal financial results and growth should also be explored.

Exploração de séries temporais em processos de previsão de vendas

Dissertação de mestrado em Engenharia de Sistemas

A continuum anisotropic model of sea-ice dynamics

We develop the essential ingredients of a new, continuum and anisotropic model of sea-ice dynamics designed for eventual use in climate simulation. These ingredients are a constitutive law for sea-ice stress, relating stress to the material properties of sea ice and to internal variables describing the sea-ice state, and equations describing the evolution of these variables. The sea-ice cover is treated as a densely flawed two-dimensional continuum consisting of a uniform field of thick ice that is uniformly permeated with narrow linear regions of thinner ice called leads. Lead orientation, thickness and width distributions are described by second-rank tensor internal variables: the structure, thickness and width tensors, whose dynamics are governed by corresponding evolution equations accounting for processes such as new lead generation and rotation as the ice cover deforms. These evolution equations contain contractions of higher-order tensor expressions that require closures. We develop a sea-ice stress constitutive law that relates sea-ice stress to the structure tensor, thickness tensor and strain rate. For the special case of empty leads (containing no ice), linear closures are adopted and we present calculations for simple shear, convergence and divergence.

An anisotropic linear elastic boundary element formulation for masonry wall analysis

This work presents an application of a Boundary Element Method (BEM) formulation for anisotropic body analysis using isotropic fundamental solution. The anisotropy is considered by expressing a residual elastic tensor as the difference of the anisotropic and isotropic elastic tensors. Internal variables and cell discretization of the domain are considered. Masonry is a composite material consisting of bricks (masonry units), mortar and the bond between them and it is necessary to take account of anisotropy in this type of structure. The paper presents the formulation, the elastic tensor of the anisotropic medium properties and the algebraic procedure. Two examples are shown to validate the formulation and good agreement was obtained when comparing analytical and numerical results. Two further examples in which masonry walls were simulated, are used to demonstrate that the presented formulation shows close agreement between BE numerical results and different Finite Element (FE) models. © 2012 Elsevier Ltd.

A BOUNDARY ELEMENT FORMULATION FOR MASONRY WALLS: NON-LINEAR ANALYSIS

In this work, a non-linear Boundary Element Method (BEM) formulation with damage model is extended for numerical simulation of structural masonry walls in 2D stress analysis. The formulation is reoriented to analyse structural masonry, the component materials of which, clay bricks and mortar, are considered as damaged materials. Also considered are the internal variables and cell discretization of the domain. A damage model is used to represent the material behaviour and the domain discretization is also proposed and discussed. The paper presents the numerical parameters of the damage model for the material properties of the masonry components, clay bricks and mortar. Some examples are shown to validate the formulation.

Active fibre-reinforced composites with embedded shape memory alloys

This dissertation concerns active fibre-reinforced composites with embedded shape memory alloy wires. The structural application of active materials allows to develop adaptive structures which actively respond to changes in the environment, such as morphing structures, self-healing structures and power harvesting devices. In particular, shape memory alloy actuators integrated within a composite actively control the structural shape or stiffness, thus influencing the composite static and dynamic properties. Envisaged applications include, among others, the prevention of thermal buckling of the outer skin of air vehicles, shape changes in panels for improved aerodynamic characteristics and the deployment of large space structures. The study and design of active composites is a complex and multidisciplinary topic, requiring in-depth understanding of both the coupled behaviour of active materials and the interaction between the different composite constituents. Both fibre-reinforced composites and shape memory alloys are extremely active research topics, whose modelling and experimental characterisation still present a number of open problems. Thus, while this dissertation focuses on active composites, some of the research results presented here can be usefully applied to traditional fibre-reinforced composites or other shape memory alloy applications. The dissertation is composed of four chapters. In the first chapter, active fibre-reinforced composites are introduced by giving an overview of the most common choices available for the reinforcement, matrix and production process, together with a brief introduction and classification of active materials. The second chapter presents a number of original contributions regarding the modelling of fibre-reinforced composites. Different two-dimensional laminate theories are derived from a parent three-dimensional theory, introducing a procedure for the a posteriori reconstruction of transverse stresses along the laminate thickness. Accurate through the thickness stresses are crucial for the composite modelling as they are responsible for some common failure mechanisms. A new finite element based on the First-order Shear Deformation Theory and a hybrid stress approach is proposed for the numerical solution of the two-dimensional laminate problem. The element is simple and computationally efficient. The transverse stresses through the laminate thickness are reconstructed starting from a general finite element solution. A two stages procedure is devised, based on Recovery by Compatibility in Patches and three-dimensional equilibrium. Finally, the determination of the elastic parameters of laminated structures via numerical-experimental Bayesian techniques is investigated. Two different estimators are analysed and compared, leading to the definition of an alternative procedure to improve convergence of the estimation process. The third chapter focuses on shape memory alloys, describing their properties and applications. A number of constitutive models proposed in the literature, both one-dimensional and three-dimensional, are critically discussed and compared, underlining their potential and limitations, which are mainly related to the definition of the phase diagram and the choice of internal variables. Some new experimental results on shape memory alloy material characterisation are also presented. These experimental observations display some features of the shape memory alloy behaviour which are generally not included in the current models, thus some ideas are proposed for the development of a new constitutive model. The fourth chapter, finally, focuses on active composite plates with embedded shape memory alloy wires. A number of di®erent approaches can be used to predict the behaviour of such structures, each model presenting different advantages and drawbacks related to complexity and versatility. A simple model able to describe both shape and stiffness control configurations within the same context is proposed and implemented. The model is then validated considering the shape control configuration, which is the most sensitive to model parameters. The experimental work is divided in two parts. In the first part, an active composite is built by gluing prestrained shape memory alloy wires on a carbon fibre laminate strip. This structure is relatively simple to build, however it is useful in order to experimentally demonstrate the feasibility of the concept proposed in the first part of the chapter. In the second part, the making of a fibre-reinforced composite with embedded shape memory alloy wires is investigated, considering different possible choices of materials and manufacturing processes. Although a number of technological issues still need to be faced, the experimental results allow to demonstrate the mechanism of shape control via embedded shape memory alloy wires, while showing a good agreement with the proposed model predictions.

Assembly and characterization of supramolecular architectures for biosensor applications

The research has included the efforts in designing, assembling and structurally and functionally characterizing supramolecular biofunctional architectures for optical biosensing applications. In the first part of the study, a class of interfaces based on the biotin-NeutrAvidin binding matrix for the quantitative control of enzyme surface coverage and activity was developed. Genetically modified ß-lactamase was chosen as a model enzyme and attached to five different types of NeutrAvidin-functionalized chip surfaces through a biotinylated spacer. All matrices are suitable for achieving a controlled enzyme surface density. Data obtained by SPR are in excellent agreement with those derived from optical waveguide measurements. Among the various protein-binding strategies investigated in this study, it was found that stiffness and order between alkanethiol-based SAMs and PEGylated surfaces are very important. Matrix D based on a Nb2O5 coating showed a satisfactory regeneration possibility. The surface-immobilized enzymes were found to be stable and sufficiently active enough for a catalytic activity assay. Many factors, such as the steric crowding effect of surface-attached enzymes, the electrostatic interaction between the negatively charged substrate (Nitrocefin) and the polycationic PLL-g-PEG/PEG-Biotin polymer, mass transport effect, and enzyme orientation, are shown to influence the kinetic parameters of catalytic analysis. Furthermore, a home-built Surface Plasmon Resonance Spectrometer of SPR and a commercial miniature Fiber Optic Absorbance Spectrometer (FOAS), served as a combination set-up for affinity and catalytic biosensor, respectively. The parallel measurements offer the opportunity of on-line activity detection of surface attached enzymes. The immobilized enzyme does not have to be in contact with the catalytic biosensor. The SPR chip can easily be cleaned and used for recycling. Additionally, with regard to the application of FOAS, the integrated SPR technique allows for the quantitative control of the surface density of the enzyme, which is highly relevant for the enzymatic activity. Finally, the miniaturized portable FOAS devices can easily be combined as an add-on device with many other in situ interfacial detection techniques, such as optical waveguide lightmode spectroscopy (OWLS), the quartz crystal microbalance (QCM) measurements, or impedance spectroscopy (IS). Surface plasmon field-enhanced fluorescence spectroscopy (SPFS) allows for an absolute determination of intrinsic rate constants describing the true parameters that control interfacial hybridization. Thus it also allows for a study of the difference of the surface coupling influences between OMCVD gold particles and planar metal films presented in the second part. The multilayer growth process was found to proceed similarly to the way it occurs on planar metal substrates. In contrast to planar bulk metal surfaces, metal colloids exhibit a narrow UV-vis absorption band. This absorption band is observed if the incident photon frequency is resonant with the collective oscillation of the conduction electrons and is known as the localized surface plasmon resonance (LSPR). LSPR excitation results in extremely large molar extinction coefficients, which are due to a combination of both absorption and scattering. When considering metal-enhanced fluorescence we expect the absorption to cause quenching and the scattering to cause enhancement. Our further study will focus on the developing of a detection platform with larger gold particles, which will display a dominant scattering component and enhance the fluorescence signal. Furthermore, the results of sequence-specific detection of DNA hybridization based on OMCVD gold particles provide an excellent application potential for this kind of cheap, simple, and mild preparation protocol applied in this gold fabrication method. In the final chapter, SPFS was used for the in-depth characterizations of the conformational changes of commercial carboxymethyl dextran (CMD) substrate induced by pH and ionic strength variations were studied using surface plasmon resonance spectroscopy. The pH response of CMD is due to the changes in the electrostatics of the system between its protonated and deprotonated forms, while the ionic strength response is attributed from the charge screening effect of the cations that shield the charge of the carboxyl groups and prevent an efficient electrostatic repulsion. Additional studies were performed using SPFS with the aim of fluorophore labeling the carboxymethyl groups. CMD matrices showed typical pH and ionic strength responses, such as high pH and low ionic strength swelling. Furthermore, the effects of the surface charge and the crosslink density of the CMD matrix on the extent of stimuli responses were investigated. The swelling/collapse ratio decreased with decreasing surface concentration of the carboxyl groups and increasing crosslink density. The study of the CMD responses to external and internal variables will provide valuable background information for practical applications.

A robust numerical framework for the analysis of material failure of fibre reinforced soft tissue

In this work, robustness and stability of continuum damage models applied to material failure in soft tissues are addressed. In the implicit damage models equipped with softening, the presence of negative eigenvalues in the tangent elemental matrix degrades the condition number of the global matrix, leading to a reduction of the computational performance of the numerical model. Two strategies have been adapted from literature to improve the aforementioned computational performance degradation: the IMPL-EX integration scheme [Oliver,2006], which renders the elemental matrix contribution definite positive, and arclength-type continuation methods [Carrera,1994], which allow to capture the unstable softening branch in brittle ruptures. The IMPL-EX integration scheme has as a major drawback the need to use small time steps to keep numerical error below an acceptable value. A convergence study, limiting the maximum allowed increment of internal variables in the damage model, is presented. Finally, numerical simulation of failure problems with fibre reinforced materials illustrates the performance of the adopted methodology.

A robust numerical framework to the analysis of material failure of fibre reinforced soft tissue

In this work, robustness and stability of continuum damage models applied to material failure in soft tissues are addressed. In the implicit damage models equipped with softening, the presence of negative eigenvalues in the tangent elemental matrix degrades the condition number of the global matrix, leading to a reduction of the computational performance of the numerical model. Two strategies have been adapted from literature to improve the aforementioned computational performance degradation: the IMPL-EX integration scheme [Oliver,2006], which renders the elemental matrix contribution definite positive, and arclength-type continuation methods [Carrera,1994], which allow to capture the unstable softening branch in brittle ruptures. The IMPL-EX integration scheme has as a major drawback the need to use small time steps to keep numerical error below an acceptable value. A convergence study, limiting the maximum allowed increment of internal variables in the damage model, is presented. Finally, numerical simulation of failure problems with fibre reinforced materials illustrates the performance of the adopted methodology.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

Modelización tridimensional de ensayos de adherencia tipo viga del refuerzo NSM-FRP en hormigón

El uso de refuerzos NSM‐FRP en estructuras de hormigón armado se ha incrementado considerablemente en los últimos años como método de refuerzo estructural. Los ensayos de arrancamiento en viga de los refuerzos NSM‐FRP permiten el estudio del comportamiento de la unión pegada. El principal objetivo del presente trabajo aborda la simulación numérica de este tipo de ensayos, con el propósito de caracterizar correctamente la adherencia entre las barras de NSM‐FRP y el hormigón. En una fase inicial se simuló un modelo bidimensional para conseguir evaluar y verificar el comportamiento de los elementos cohesivos y ver su comportamiento primero ante diferentes modelos de material y segundo ante un modo mixto de fallo, debido a la aplicación simultanea de carga axial y carga cortante. En una segunda fase se creó un modelo tridimensional para estudiar el arrancamiento de una barra de material compuesto insertada en hormigón, creando un modelo de material de hormigón y viendo el comportamiento cualitativo del sistema ante variaciones en los parámetros de los diferentes materiales. En la tercera fase, la más importante del presente trabajo, se abordó la simulación numérica del ensayo de arrancamiento en viga. Se simularon todos los componentes del ensayo y se evaluaron diferentes alternativas para representar la interfase NSM‐FRP ‐ hormigón, usando elementos cohesivos y diferentes distribuciones de los mismos en la interfase. Para conseguir representar lo más fielmente posible las condiciones del ensayo, se diseñó también un controlador PID que permite realizar las simulaciones numéricas mediante un control en desplazamientos, lo cual permite capturar más correctamente el comportamiento de reblandecimiento de la unión pegada. El controlador PID aplica técnicas de ingeniería de control para conseguir calcular a priori la amplitud necesaria del desplazamiento impuesto que provoque una evolución establecida en una variable interna del sistema. La variable usada para correlacionar los ensayos es la diferencia en desplazamientos entre dos puntos y se escoge una evolución lineal de la misma, pero en la tesis también se exponen los resultados de escoger otras posibles variables internas con diferentes evoluciones. Se compararon las simulaciones numéricas con resultados de mediciones experimentales previamente publicadas. Los resultados carga‐deslizamiento obtenidos encajan bien con los datos experimentales. El modelo propuesto es también capaz de predecir el modo de fallo en la interfase NSM‐FRP ‐ hormigón. Finalmente, también se han llevado a cabo estudios paramétricos, para evaluar la influencia de cada parámetro en los resultados. También se realizó un estudio cualitativo de cómo se comporta la unión pegada en cada momento de la simulación, mediante el uso macros y gráficas tridimensionales, para conseguir una mejor visualización y facilitar el análisis de los resultados. ABSTRACT The use of near‐surface mounted FRP reinforcement in reinforced concrete structures has seen a considerable increase in recent years as a strengthening method. Beam pull‐out tests for near‐surface reinforcement allow obtaining the local bond‐slip behavior of a bonded joint. The main objective of the current work deals with the three‐dimensional modeling of this kind of test with the purpose of characterizing suitably the mechanics of bond between FRP rods and concrete. In an initial stage, a two bidimensional in order to evaluate and to verify the behavior of the cohesive elements. Its behavior was evaluated first testing different material models and second testing the behavior when mixed mode failure appears, due to simultaneous axial and shear load. In a second stage a tridimensional model was created in order to study the pull‐out of an inserted beam of composite material in concrete. A concrete material model was created and the influence of each material parameter was studied qualitatively. The third part, the most relevant of the present work, the numerical simulation of the Beam Pull‐Out test was faced. All the parts of the Beam Pull‐Out test were included inthe simulation and different alternatives to represent the FRP bar – concrete interface have been evaluated, using cohesive elements and different distributions of them. In order to reproduce the test conditions more reliably, a PID controller has also been designed to conduct suitably the numerical tests in order to properly capture the softening branch of the load‐slip behaviour. The PID controller applies control techniques to calculate a priori the necessary amplitude of the load in order to achieve a given evolution through the simulation of an internal variable previously chosen. The variable used in order to correlate the simulation with the test results is the difference in displacements between two points and a linear evolution was chosen, but in the thesis the results of choosing other possible internal variables with different evolutions are also shown. The numerical FE simulations were compared with experimental measurements previously published. Load‐slip predictions compare well with the corresponding experimental data. The proposed model is also able to predict the failure mode at the FRP‐concrete interface. Some parametric studies have also been carried out, in order to evaluate the influence of each material parameter in the results. A qualitative study of the behaviour of the joint was also performed, using the results of the numeric simulations and through the use of macros and 3D graphs, the tensional state of each point of the joint can be visualized in each moment of the simulation.

An analysis of changing management roles in small Australian services exporters in response to the stages in industry development

Life cycle models have become important in explaining the changing size structure of firms based on the carrying capacity of regions or industries. In particular, the population ecology model predicts stages of growth, maturity and eventually decline in the number of firms in an industry. There has been criticism of such models because of their focus on external variables as pre-determinants of the potential for enterprise development. This paper attempts to reconcile the external focus of the population ecology model with relevant internal management factors in enterprise development. A survey was conducted of Australian services exporters, and the results not only confirm the existence of four separate life cycle stages in the population ecology model, but also identify the external and internal variables that are strategically relevant at each of the stages. The findings provide potentially useful information in a range of contexts including the design of small business assistance as well a providing “guide posts” to entrepreneurs engaged in enterprise development.

The behaviour of granular material in pure shear, direct shear and simple shear

In biaxial compression tests, the stress calculations based on boundary information underestimate the principal stresses leading to a significant overestimation of the shear strength. In direct shear tests, the shear strain becomes highly concentrated in the mid-plane of the sample during the test. Although the stress distribution within the specimen is heterogeneous, the evolution of the stress ratio inside the shear band is similar to that inferred from the boundary force calculations. It is also demonstrated that the dilatancy in the shear band significantly exceeds that implied from the boundary displacements. In simple shear tests, the stresses acting on the wall boundaries do not reflect the internal state of stress but merely provide information about the average mobilised wall friction. It is demonstrated that the results are sensitive to the initial stress state defined by K0 = sh/sv. For all cases, non-coaxiality of the principal stress and strain-rate directions is examined and the corresponding flow rule is identified. Periodic cell simulations have been used to examine biaxial compression for a wide range of initial packing densities. Both constant volume and constant mean stress tests have been simulated. The characteristic behaviour at both the macroscopic and microscopic scales is determined by whether or not the system percolates (enduring connectivity is established in all directions). The transition from non-percolating to percolating systems is characterised by transitional behaviour of internal variables and corresponds to an elastic percolation threshold, which correlates well with the establishment of a mechanical coordination number of ca. 3.0. Strong correlations are found between macroscopic and internal variables at the critical state.