Computer Aided Design Algorithmic Technique for Very Large Scale Integrated Circuit Design and Smart Home Embedded System Design

To tackle the challenges at circuit level and system level VLSI and embedded system design, this dissertation proposes various novel algorithms to explore the efficient solutions. At the circuit level, a new reliability-driven minimum cost Steiner routing and layer assignment scheme is proposed, and the first transceiver insertion algorithmic framework for the optical interconnect is proposed. At the system level, a reliability-driven task scheduling scheme for multiprocessor real-time embedded systems, which optimizes system energy consumption under stochastic fault occurrences, is proposed. The embedded system design is also widely used in the smart home area for improving health, wellbeing and quality of life. The proposed scheduling scheme for multiprocessor embedded systems is hence extended to handle the energy consumption scheduling issues for smart homes. The extended scheme can arrange the household appliances for operation to minimize monetary expense of a customer based on the time-varying pricing model.

Modeling of integrated inductors for RF circuit design

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica

A new chemorheological analysis of highly filled thermosets used in integrated circuit packaging

Chemorheology (and thus process modeling) of highly filled thermosets used in integrated circuit (IC) packaging has been complicated by their highly filled nature, fast kinetics of curing, and viscoelastic nature. This article summarizes a more thorough chemorheological analysis of a typical IC packaging thermoset material, including novel isothermal and nonisothermal multiwave parallel-plate chemorheology. This new chemorheological analysis may be used to optimize existing and design new IC packaging processes. (C) 1997 John Wiley & Sons, Inc.

Flow-through cell based on an array of gold microelectrodes obtained from modified integrated circuit chips

The construction of a flow-through cell incorporating an array of gold microelectrodes is described and its application to flow injection analysis with amperometric detection is presented, Simple modification of almost any conventional integrated circuit chip, used as an inexpensive source of pre-assembled gold micro-wires, leads to the rapid and successful preparation of arrays of 8-48 elements, the polymeric encapsulation material from the top face of the chip is removed by abrasion until the gold micro-mires (used to interconnect the silicon circuit to the external contact pins of the chip) are disrupted and their transversal (elliptical) sections become exposed. Once polished, the flat and smooth top surface of the gold microelectrode-array chip (MEAC) is provided with a spacer and fitted under pressure against an acrylic block with the reference and auxiliary electrodes, to form the electrochemical (thin-layer) flow cell, while the contact pins are plugged into a standard IC socket, This design ensures autonomous electric contact with each electrode and allows fast dismantling for polishing or substitution, the performance of flow cells with MEACs was investigated utilizing the technique of reverse pulse amperometry without oxygen removal, A method was established for the determination of the copper concentration in sugar cane spirit, regulated by law for beverages, Samples from industrial producers and small-scale (alembic) brewers were compared, With a 24 MEAC, a detection limit of 30 mu g I-l of copper (4.7 x 10(-7) mol l(-1) of Cu-II for 100 mu l injections) was calculated, Routine operation was established at a frequency of 60-90 determinations per hour, Intercomparison with atomic absorption spectrometric determinations resulted in excellent agreement.

Methodology analysis of a computational tool used in electronic circuit design

This paper considers the importance of using a top-down methodology and suitable CAD tools in the development of electronic circuits. The paper presents an evaluation of the methodology used in a computational tool created to support the synthesis of digital to analog converter models by translating between different tools used in a wide variety of applications. This tool is named MS 2SV and works directly with the following two commercial tools: MATLAB/Simulink and SystemVision. Model translation of an electronic circuit is achieved by translating a mixed-signal block diagram developed in Simulink into a lower level of abstraction in VHDL-AMS and the simulation project support structure in SystemVision. The method validation was performed by analyzing the power spectral of the signal obtained by the discrete Fourier transform of a digital to analog converter simulation model. © 2011 IEEE.

Feasible Dose Reduction in Routine Chest Computed Tomography Maintaining Constant Image Quality Using the Last Three Scanner Generations: From Filtered Back Projection to Sinogram-affirmed Iterative Reconstruction and Impact of the Novel Fully Integrated Detector Design Minimizing Electronic Noise

OBJECTIVE The aim of the present study was to evaluate a dose reduction in contrast-enhanced chest computed tomography (CT) by comparing the three latest generations of Siemens CT scanners used in clinical practice. We analyzed the amount of radiation used with filtered back projection (FBP) and an iterative reconstruction (IR) algorithm to yield the same image quality. Furthermore, the influence on the radiation dose of the most recent integrated circuit detector (ICD; Stellar detector, Siemens Healthcare, Erlangen, Germany) was investigated. MATERIALS AND METHODS 136 Patients were included. Scan parameters were set to a thorax routine: SOMATOM Sensation 64 (FBP), SOMATOM Definition Flash (IR), and SOMATOM Definition Edge (ICD and IR). Tube current was set constantly to the reference level of 100 mA automated tube current modulation using reference milliamperes. Care kV was used on the Flash and Edge scanner, while tube potential was individually selected between 100 and 140 kVp by the medical technologists at the SOMATOM Sensation. Quality assessment was performed on soft-tissue kernel reconstruction. Dose was represented by the dose length product. RESULTS Dose-length product (DLP) with FBP for the average chest CT was 308 mGy*cm ± 99.6. In contrast, the DLP for the chest CT with IR algorithm was 196.8 mGy*cm ± 68.8 (P = 0.0001). Further decline in dose can be noted with IR and the ICD: DLP: 166.4 mGy*cm ± 54.5 (P = 0.033). The dose reduction compared to FBP was 36.1% with IR and 45.6% with IR/ICD. Signal-to-noise ratio (SNR) was favorable in the aorta, bone, and soft tissue for IR/ICD in combination compared to FBP (the P values ranged from 0.003 to 0.048). Overall contrast-to-noise ratio (CNR) improved with declining DLP. CONCLUSION The most recent technical developments, namely IR in combination with integrated circuit detectors, can significantly lower radiation dose in chest CT examinations.

Chemical studies of plasma etchants used in integrated circuit manufacture

Plasma or "dry" etching is an essential process for the production of modern microelectronic circuits. However, despite intensive research, many aspects of the etch process are not fully understood. The results of studies of the plasma etching of Si and Si02 in fluorine-containing discharges, and the complementary technique of plasma polymerisation are presented in this thesis. Optical emission spectroscopy with argon actinometry was used as the principle plasma diagnostic. Statistical experimental design was used to model and compare Si and Si02 etch rates in CF4 and SF6 discharges as a function of flow, pressure and power. Etch mechanisms m both systems, including the potential reduction of Si etch rates in CF4 due to fluorocarbon polymer formation, are discussed. Si etch rates in CF4 /SF6 mixtures were successfully accounted for by the models produced. Si etch rates in CF4/C2F6 and CHF3 as a function of the addition of oxygen-containing additives (02, N20 and CO2) are shown to be consistent with a simple competition between F, 0 and CFx species for Si surface sites. For the range of conditions studied, Si02 etch rates were not dependent on F-atom concentration, but the presence of fluorine was essential in order to achieve significant etch rates. The influence of a wide range of electrode materials on the etch rate of Si and Si02 in CF4 and CF4 /02 plasmas was studied. It was found that the Si etch rate in a CF4 plasma was considerably enhanced, relative to an anodised aluminium electrode, in the presence of soda glass or sodium or potassium "doped" quartz. The effect was even more pronounced in a CF4 /02 discharge. In the latter system lead and copper electrodes also enhanced the Si etch rate. These results could not be accounted for by a corresponding rise in atomic fluorine concentration. Three possible etch enhancement mechanisms are discussed. Fluorocarbon polymer deposition was studied, both because of its relevance to etch mechanisms and its intrinsic interest, as a function of fluorocarbon source gas (CF4, C2F6, C3F8 and CHF3), process time, RF power and percentage hydrogen addition. Gas phase concentrations of F, H and CF2 were measured by optical emission spectroscopy, and the resultant polymer structure determined by X-ray photoelectron spectroscopy and infrared spectroscopy. Thermal and electrical properties were measured also. Hydrogen additions are shown to have a dominant role in determining deposition rate and polymer composition. A qualitative description of the polymer growth mechanism is presented which accounts for both changes in growth rate and structure, and leads to an empirical deposition rate model.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

Arrays of gold microelectrodes made from split integrated circuit chips

A simple and inexpensive way to fabricate arrays of gold microelectrodes is proposed. Integrated circuit chips are sawed through their middle, normal to the longest axis, leading to destruction of the silicon circuit and rupture of the gold wires that interconnect it with the external terminals. Polishing the resulting rough surface converts the tips of the wires embedded in the chip halves into arrays of gold microdisks of about 25 mu m diameter. The number of active microelectrodes (MEs), of an array depends on the number of pins in the chip, n, being typically (n/2)-4. These MEs can be used individually or externally interconnected in any combination. X-ray images of the chips and micrographs of the resulting surface of the polished arrays have revealed variable distances between neighbor MEs, which are, however, larger than 10 times the radius of the disks. This feature of the MEs prevents diffusional cross-talk between electrodes. The use of these microdisk electrodes for analytical purposes exhibits sigmoidal voltammograms, and chronoamperometric experiments confirm the nonlinear i vs. t(1/2) plots, typical for processes where radial diffusion prevails. Satisfactory uniformity was observed for the response of each electrode of an array, indicating similarity of geometry and disk areas. The potentialities of these MEs were demonstrated by the determination of cadmium at ppb levels using square wave voltammetry with preconcentration. Due to the relative ease with which these MEs can be manufactured and their good performance in (chemical) analysis, wide applications in electrochemistry and electroanalysis is envisioned.

Electrothermal characterization and nonlinear modelling of GaN transistors for telecommunication circuit design

This thesis starts showing the main characteristics and application fields of the AlGaN/GaN HEMT technology, focusing on reliability aspects essentially due to the presence of low frequency dispersive phenomena which limit in several ways the microwave performance of this kind of devices. Based on an equivalent voltage approach, a new low frequency device model is presented where the dynamic nonlinearity of the trapping effect is taken into account for the first time allowing considerable improvements in the prediction of very important quantities for the design of power amplifier such as power added efficiency, dissipated power and internal device temperature. An innovative and low-cost measurement setup for the characterization of the device under low-frequency large-amplitude sinusoidal excitation is also presented. This setup allows the identification of the new low frequency model through suitable procedures explained in detail. In this thesis a new non-invasive empirical method for compact electrothermal modeling and thermal resistance extraction is also described. The new contribution of the proposed approach concerns the non linear dependence of the channel temperature on the dissipated power. This is very important for GaN devices since they are capable of operating at relatively high temperatures with high power densities and the dependence of the thermal resistance on the temperature is quite relevant. Finally a novel method for the device thermal simulation is investigated: based on the analytical solution of the tree-dimensional heat equation, a Visual Basic program has been developed to estimate, in real time, the temperature distribution on the hottest surface of planar multilayer structures. The developed solver is particularly useful for peak temperature estimation at the design stage when critical decisions about circuit design and packaging have to be made. It facilitates the layout optimization and reliability improvement, allowing the correct choice of the device geometry and configuration to achieve the best possible thermal performance.