734 resultados para Higher circuit
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Los procesos sociales, económicos y productivos que tienen lugar en el territorio y en las ciudades de Argentina, en el actual periodo de la globalización, pueden comprenderse a partir de la teoría de los circuitos de la economía urbana (Santos, 1975, 1979). La coexistencia de divisiones territoriales del trabajo en la ciudad explicaría la presencia de un circuito superior y un circuito inferior que, de diferentes maneras, son resultado de la modernización tecnológica y cumplen un papel importante en el proceso económico y en el proceso de organización del espacio. Se analiza el papel del sistema financiero de crédito como un vínculo de unión entre ambos circuitos. Se examinan los diferentes instrumentos financieros que posibilitan la financierización de la sociedad y el territorio, junto a los diversos efectos del crédito y del consumo en la ciudad de Olavarría
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Los procesos sociales, económicos y productivos que tienen lugar en el territorio y en las ciudades de Argentina, en el actual periodo de la globalización, pueden comprenderse a partir de la teoría de los circuitos de la economía urbana (Santos, 1975, 1979). La coexistencia de divisiones territoriales del trabajo en la ciudad explicaría la presencia de un circuito superior y un circuito inferior que, de diferentes maneras, son resultado de la modernización tecnológica y cumplen un papel importante en el proceso económico y en el proceso de organización del espacio. Se analiza el papel del sistema financiero de crédito como un vínculo de unión entre ambos circuitos. Se examinan los diferentes instrumentos financieros que posibilitan la financierización de la sociedad y el territorio, junto a los diversos efectos del crédito y del consumo en la ciudad de Olavarría
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Los procesos sociales, económicos y productivos que tienen lugar en el territorio y en las ciudades de Argentina, en el actual periodo de la globalización, pueden comprenderse a partir de la teoría de los circuitos de la economía urbana (Santos, 1975, 1979). La coexistencia de divisiones territoriales del trabajo en la ciudad explicaría la presencia de un circuito superior y un circuito inferior que, de diferentes maneras, son resultado de la modernización tecnológica y cumplen un papel importante en el proceso económico y en el proceso de organización del espacio. Se analiza el papel del sistema financiero de crédito como un vínculo de unión entre ambos circuitos. Se examinan los diferentes instrumentos financieros que posibilitan la financierización de la sociedad y el territorio, junto a los diversos efectos del crédito y del consumo en la ciudad de Olavarría
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Aim. The purpose of present study was to compare the acute physiological responses to a circuit weight training with the responses to a combined circuit training (weight training and treadmill run). Methods. The sample consisted of 25 individuals at an average state of training, 10 men and 15 female, between 18 and 35 year old. There were selected 60 second sets of resistance exercises to the circuit weight training (CWT). Whereas in the combined circuit training (CCT), the subjects spent 30 seconds on the same resistance exercises and 30 seconds running on the treadmill. The rest intervals between the sets lasted 15 seconds. The analysis of variance (ANOVA) with 5% significance level was utilized to the statistical analysis of the results. Results. Comparing circuit training protocols, it was noted that CCT elicits a higher relative and absolute <(V)over dot>O(2) and energy expenditure values than CWT for both genders (P<0.05). Regarding inter-gender comparison, males showed higher absolute and relative <(V)over dot>O(2) and absolute energy expenditure values for both CWT and CCT than females (P<0.05). Females showed a significant greater % <(V)over dot>O(2max) value for both CWT and CCT. Due to the experimental conditions used to state both circuit training bouts (CWT and CCT), the <(V)over dot>O(2) rate found was higher than the values reported by previous studies which used heavier weight lift. Conclusion. CCT seems adequate to produce cardiovascular improvements and greater energy expenditure for both men and women, while CWT group classes are sufficient only for unfit women.
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Given the urgence of a new paradigm in wireless digital trasmission which should allow for higher bit rate, lower latency and tigher delay constaints, it has been proposed to investigate the fundamental building blocks that at the circuital/device level, will boost the change towards a more efficient network architecture, with high capacity, higher bandwidth and a more satisfactory end user experience. At the core of each transciever, there are inherently analog devices capable of providing the carrier signal, the oscillators. It is strongly believed that many limitations in today's communication protocols, could be relieved by permitting high carrier frequency radio transmission, and having some degree of reconfigurability. This led us to studying distributed oscillator architectures which work in the microwave range and possess wideband tuning capability. As microvave oscillators are essentially nonlinear devices, a full nonlinear analyis, synthesis, and optimization had to be considered for their implementation. Consequently, all the most used nonlinear numerical techniques in commercial EDA software had been reviewed. An application of all the aforementioned techniques has been shown, considering a systems of three coupled oscillator ("triple push" oscillator) in which the stability of the various oscillating modes has been studied. Provided that a certain phase distribution is maintained among the oscillating elements, this topology permits a rise in the output power of the third harmonic; nevertheless due to circuit simmetry, "unwanted" oscillating modes coexist with the intenteded one. Starting with the necessary background on distributed amplification and distributed oscillator theory, the design of a four stage reverse mode distributed voltage controlled oscillator (DVCO) using lumped elments has been presented. All the design steps have been reported and for the first time a method for an optimized design with reduced variations in the output power has been presented. Ongoing work is devoted to model a wideband DVCO and to implement a frequency divider.
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The effects of mucosally added Escherichia coli heat stable enterotoxin (STa 30 ng ml-1) on the basal short-circuit current (Isc in µA cm-2) across stripped and unstripped sheets of jejuna and ilea taken from fed, starved (4 days, water ad lib) and undernourished (50% control food intake for 21 days) gerbil (Gerbillus cheesmani) were investigated. The effect of neurotoxin tetrodotoxin (TTX 10 µM) and the effects of replacing chloride by gluconate or the effects of removing bicarbonate from bathing buffers on the maximum increase in Isc induced by STa were also investigated. The maximum increase in Isc which resulted from the addition of STa were significantly higher in jejuna and ilea taken from starved and undernourished gerbils when compared with the fed control both using stripped and unstripped sheets. In the two regions of the small intestine taken from fed and starved animals TTX reduced the maximum increase in Isc induced by STa across unstripped sheets only. Moreover in jejuna and ilea taken from undernourished gerbils TTX reduced significantly the maximum increase in Isc induced by STa across stripped and unstripped sheets. Replacing chloride by gluconate decreased the maximum increase in Isc induced by STa across jejuna and ilea taken from undernourished gerbils only. Removing bicarbonates from bathing buffer decreased the maximum increase in Isc across the jejuna and ilea taken from starved and undernourished gerbils.
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OBJECTIVE: Standard cardiopulmonary bypass (CPB) circuits with their large surface area and volume contribute to postoperative systemic inflammatory reaction and hemodilution. In order to minimize these problems a new approach has been developed resulting in a single disposable, compact arterio-venous loop, which has integral kinetic-assist pumping, oxygenating, air removal, and gross filtration capabilities (CardioVention Inc., Santa Clara, CA, USA). The impact of this system on gas exchange capacity, blood elements and hemolysis is compared to that of a conventional circuit in a model of prolonged perfusion. METHODS: Twelve calves (mean body weight: 72.2+/-3.7 kg) were placed on cardiopulmonary bypass for 6 h with a flow of 5 l/min, and randomly assigned to the CardioVention system (n=6) or a standard CPB circuit (n=6). A standard battery of blood samples was taken before bypass and throughout bypass. Analysis of variance was used for comparison. RESULTS: The hematocrit remained stable throughout the experiment in the CardioVention group, whereas it dropped in the standard group in the early phase of perfusion. When normalized for prebypass values, both profiles differed significantly (P<0.01). Both O2 and CO2 transfers were significantly improved in the CardioVention group (P=0.04 and P<0.001, respectively). There was a slightly higher pressure drop in the CardioVention group but no single value exceeded 112 mmHg. No hemolysis could be detected in either group with all free plasma Hb values below 15 mg/l. Thrombocyte count, when corrected by hematocrit and normalized by prebypass values, exhibited an increased drop in the standard group (P=0.03). CONCLUSION: The CardioVention system with its concept of limited priming volume and exposed foreign surface area, improves gas exchange probably because of the absence of detectable hemodilution, and appears to limit the decrease in the thrombocyte count which may be ascribed to the reduced surface. Despite the volume and surface constraints, no hemolysis could be detected throughout the 6 h full-flow perfusion period.
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Background Depression is a heterogeneous mental illness. Neurostimulation treatments, by targeting specific nodes within the brain’s emotion-regulation network, may be useful both as therapies and as probes for identifying clinically relevant depression subtypes. Methods Here, we applied 20 sessions of magnetic resonance imaging-guided repetitive transcranial magnetic stimulation (rTMS) to the dorsomedial prefrontal cortex in 47 unipolar or bipolar patients with a medication-resistant major depressive episode. Results Treatment response was strongly bimodal, with individual patients showing either minimal or marked improvement. Compared with responders, nonresponders showed markedly higher baseline anhedonia symptomatology (including pessimism, loss of pleasure, and loss of interest in previously enjoyed activities) on item-by-item examination of Beck Depression Inventory-II and Quick Inventory of Depressive Symptomatology ratings. Congruently, on baseline functional magnetic resonance imaging, nonresponders showed significantly lower connectivity through a classical reward pathway comprising ventral tegmental area, striatum, and a region in ventromedial prefrontal cortex. Responders and nonresponders also showed opposite patterns of hemispheric lateralization in the connectivity of dorsomedial and dorsolateral regions to this same ventromedial region. Conclusions The results suggest distinct depression subtypes, one with preserved hedonic function and responsive to dorsomedial rTMS and another with disrupted hedonic function, abnormally lateralized connectivity through ventromedial prefrontal cortex, and unresponsive to dorsomedial rTMS. Future research directly comparing the effects of rTMS at different targets, guided by neuroimaging and clinical presentation, may clarify whether hedonia/reward circuit integrity is a reliable marker for optimizing rTMS target selection.
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Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
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A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The architecture was implemented in a prototype of imager with 32x32 pixel array fabricated in AMS CMOS 0.35νm and was characterized for sensitivity and color response. The pixel is composed of an n+/psub photodiode, a comparator and a D flip-flop having 16% fill-factor and 30νmx26νm dimensions. The multisampling architecture requires only a 1 bit per pixel memory instead of 8 bits which is typical for time-domain active pixel architectures. The advantage is that the number of transistors in the pixel is low, saving area and providing higher fill-factor. The maximum frame rate is analyzed as a function of number of bits and array size. The analysis shows that it is possible to achieve high frame rates and operation in video mode with 10 bits. Also, we present analysis for the impact of comparator offset voltage in the fixed pattern noise. Copyright 2007 ACM.
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Aim: The aim of this study was to investigate the impact of circuit-based exercise on the body composition in obese older women by focusing on physical exercise and body weight (BW) gain control in older people. Methods: Seventy older women (>60 years old) voluntarily took part in the study. Participants were randomized into six different groups according to body mass index (BMI): appropriate weight (AW) control (AWC) and trained (AWT) groups, overweight (OW) control (OWC) and trained (OWT) groups, and obesity (O) control (OC) and trained (OT) groups. The exercise program consisted of 50 minutes of exercise three times per week for 12 weeks. The exercises were alternated between upper and lower body using rest between sets for 40 seconds with intensity controlled by heart rate (70% of work). The contraction time established was 5 seconds to eccentric and concentric muscular action phase. The following anthropometric parameters were evaluated: height (m), body weight (BW, kg), body fat (BF, %), fat mass (FM, kg), lean mass (LM, kg), and BMI (kg/m(2)). Results: The values (mean +/- standard deviation [SD]) of relative changes to BW (-8.0% +/- 0.8%), BF (-21.4% +/- 2.1%), LM (3.0% +/- 0.3%), and FM (-31.2% +/- 3.0%) to the OT group were higher (P < .05) than in the AWT (BW: -2.0% +/- 1.1%; BF: -4.6% +/- 1.8%; FM: -7.0% +/- 2.8%; LM: 0.2% +/- 1.1%) and OWT (BW: -4.5% +/- 1.0%; BF: -11.0% +/- 2.2%; FM: -16.1% +/- 3.2%; LM: -0.2% +/- 1.0%) groups; additionally, no differences were found for C groups. While reduction (P < .03) in BMI according to absolute values was observed for all trained groups (AWT: 22 +/- 1 versus 21 +/- 1; OWT: 27 +/- 1 versus 25 +/- 1, OT: 34 +/- 1 versus 30 +/- 1) after training, no differences were found for C groups. Conclusion: In summary, circuit-based exercise is an effective method for promoting reduction in anthropometrics parameters in obese older women.
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Inductive-capacitive (LC) resonant circuit sensors are low-cost, wireless, durable, simple to fabricate and battery-less. Consequently, they are well suited to sensing applications in harsh environments or in situations where large numbers of sensors are needed. They are also advantageous in applications where access to the sensor is limited or impossible or when sensors are needed on a disposable basis. Due to their many advantages, LC sensors have been used for sensing a variety of parameters including humidity, temperature, chemical concentrations, pH, stress/pressure, strain, food quality and even biological growth. However, current versions of the LC sensor technology are limited to sensing only one parameter. The purpose of this work is to develop new types of LC sensor systems that are simpler to fabricate (hence lower cost) or capable of monitoring multiple parameters simultaneously. One design presented in this work, referred to as the multi-element LC sensor, is able to measure multiple parameters simultaneously using a second capacitive element. Compared to conventional LC sensors, this design can sense multiple parameters with a higher detection range than two independent sensors while maintaining the same overall sensor footprint. In addition, the two-element sensor does not suffer from interference issues normally encountered while implementing two LC sensors in close proximity. Another design, the single-spiral inductive-capacitive sensor, utilizes the parasitic capacitance of a coil or spring structure to form a single layer LC resonant circuit. Unlike conventional LC sensors, this design is truly planar, thus simplifying its fabrication process and reducing sensor cost. Due to the simplicity of this sensor layout it will be easier and more cost-effective for embedding in common building or packaging materials during manufacturing processes, thereby adding functionality to current products (such as drywall sheets) while having a minor impact on overall unit cost. These modifications to the LC sensor design significantly improve the functionality and commercial feasibility of this technology, especially for applications where a large array of sensors or multiple sensing parameters are required.
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This paper describes a technique to significantly improve upon the mass peak shape and mass resolution of spaceborne quadrupolemass spectrometers (QMSs) through higher order auxiliary excitation of the quadrupole field. Using a novel multiresonant tank circuit, additional frequency components can be used to drive modulating voltages on the quadrupole rods in a practical manner, suitable for both improved commercial applications and spaceflight instruments. Auxiliary excitation at frequencies near twice that of the fundamental quadrupole RF frequency provides the advantages of previously studied parametric excitation techniques, but with the added benefit of increased sensed excitation amplitude dynamic range and the ability to operate voltage scan lines through the center of upper stability islands. Using a field programmable gate array, the amplitudes and frequencies of all QMS signals are digitally generated and managed, providing a robust and stable voltage control system. These techniques are experimentally verified through an interface with a commercial Pfeiffer QMG422 quadrupole rod system. When operating through the center of a stability island formed from higher order auxiliary excitation, approximately 50% and 400% improvements in 1% mass resolution and peak stability were measured, respectively, when compared with traditional QMS operation. Although tested with a circular rod system, the presented techniques have the potential to improve the performance of both circular and hyperbolic rod geometry QMS sensors.
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El desarrollo da las nuevas tecnologías permite a los ingenieros llevar al límite el funcionamiento de los circuitos integrados (Integrated Circuits, IC). Las nuevas generaciones de procesadores, DSPs o FPGAs son capaces de procesar la información a una alta velocidad, con un alto consumo de energía, o esperar en modo de baja potencia con el mínimo consumo posible. Esta gran variación en el consumo de potencia y el corto tiempo necesario para cambiar de un nivel al otro, afecta a las especificaciones del Módulo de Regulador de Tensión (Voltage Regulated Module, VRM) que alimenta al IC. Además, las características adicionales obligatorias, tales como adaptación del nivel de tensión (Adaptive Voltage Positioning, AVP) y escalado dinámico de la tensión (Dynamic Voltage Scaling, DVS), imponen requisitos opuestas en el diseño de la etapa de potencia del VRM. Para poder soportar las altas variaciones de los escalones de carga, el condensador de filtro de salida del VRM se ha de sobredimensionar, penalizando la densidad de energía y el rendimiento durante la operación de DVS. Por tanto, las actuales tendencias de investigación se centran en mejorar la respuesta dinámica del VRM, mientras se reduce el tamaño del condensador de salida. La reducción del condensador de salida lleva a menor coste y una prolongación de la vida del sistema ya que se podría evitar el uso de condensadores voluminosos, normalmente implementados con condensadores OSCON. Una ventaja adicional es que reduciendo el condensador de salida, el DVS se puede realizar más rápido y con menor estrés de la etapa de potencia, ya que la cantidad de carga necesaria para cambiar la tensión de salida es menor. El comportamiento dinámico del sistema con un control lineal (Control Modo Tensión, VMC, o Control Corriente de Pico, Peak Current Mode Control, PCMC,…) está limitado por la frecuencia de conmutación del convertidor y por el tamaño del filtro de salida. La reducción del condensador de salida se puede lograr incrementando la frecuencia de conmutación, así como incrementando el ancho de banda del sistema, y/o aplicando controles avanzados no-lineales. Usando esos controles, las variables del estado se saturan para conseguir el nuevo régimen permanente en un tiempo mínimo, así como el filtro de salida, más específicamente la pendiente de la corriente de la bobina, define la respuesta de la tensión de salida. Por tanto, reduciendo la inductancia de la bobina de salida, la corriente de bobina llega más rápido al nuevo régimen permanente, por lo que una menor cantidad de carga es tomada del condensador de salida durante el tránsito. El inconveniente de esa propuesta es que el rendimiento del sistema es penalizado debido al incremento de pérdidas de conmutación y las corrientes RMS. Para conseguir tanto la reducción del condensador de salida como el alto rendimiento del sistema, mientras se satisfacen las estrictas especificaciones dinámicas, un convertidor multifase es adoptado como estándar para aplicaciones VRM. Para asegurar el reparto de las corrientes entre fases, el convertidor multifase se suele implementar con control de modo de corriente. Para superar la limitación impuesta por el filtro de salida, la segunda posibilidad para reducir el condensador de salida es aplicar alguna modificación topológica (Topologic modifications) de la etapa básica de potencia para incrementar la pendiente de la corriente de bobina y así reducir la duración de tránsito. Como el transitorio se ha reducido, una menor cantidad de carga es tomada del condensador de salida bajo el mismo escalón de la corriente de salida, con lo cual, el condensador de salida se puede reducir para lograr la misma desviación de la tensión de salida. La tercera posibilidad para reducir el condensador de salida del convertidor es introducir un camino auxiliar de energía (additional energy path, AEP) para compensar el desequilibrio de la carga del condensador de salida reduciendo consecuentemente la duración del transitorio y la desviación de la tensión de salida. De esta manera, durante el régimen permanente, el sistema tiene un alto rendimiento debido a que el convertidor principal con bajo ancho de banda es diseñado para trabajar con una frecuencia de conmutación moderada para conseguir requisitos estáticos. Por otro lado, el comportamiento dinámico durante los transitorios es determinado por el AEP con un alto ancho de banda. El AEP puede ser implementado como un camino resistivo, como regulador lineal (Linear regulator, LR) o como un convertidor conmutado. Las dos primeras implementaciones proveen un mayor ancho de banda, acosta del incremento de pérdidas durante el transitorio. Por otro lado, la implementación del convertidor computado presenta menor ancho de banda, limitado por la frecuencia de conmutación, aunque produce menores pérdidas comparado con las dos anteriores implementaciones. Dependiendo de la aplicación, la implementación y la estrategia de control del sistema, hay una variedad de soluciones propuestas en el Estado del Arte (State-of-the-Art, SoA), teniendo diferentes propiedades donde una solución ofrece más ventajas que las otras, pero también unas desventajas. En general, un sistema con AEP ideal debería tener las siguientes propiedades: 1. El impacto del AEP a las pérdidas del sistema debería ser mínimo. A lo largo de la operación, el AEP genera pérdidas adicionales, con lo cual, en el caso ideal, el AEP debería trabajar por un pequeño intervalo de tiempo, solo durante los tránsitos; la otra opción es tener el AEP constantemente activo pero, por la compensación del rizado de la corriente de bobina, se generan pérdidas innecesarias. 2. El AEP debería ser activado inmediatamente para minimizar la desviación de la tensión de salida. Para conseguir una activación casi instantánea, el sistema puede ser informado por la carga antes del escalón o el sistema puede observar la corriente del condensador de salida, debido a que es la primera variable del estado que actúa a la perturbación de la corriente de salida. De esa manera, el AEP es activado con casi cero error de la tensión de salida, logrando una menor desviación de la tensión de salida. 3. El AEP debería ser desactivado una vez que el nuevo régimen permanente es detectado para evitar los transitorios adicionales de establecimiento. La mayoría de las soluciones de SoA estiman la duración del transitorio, que puede provocar un transitorio adicional si la estimación no se ha hecho correctamente (por ejemplo, si la corriente de bobina del convertidor principal tiene un nivel superior o inferior al necesitado, el regulador lento del convertidor principal tiene que compensar esa diferencia una vez que el AEP es desactivado). Otras soluciones de SoA observan las variables de estado, asegurando que el sistema llegue al nuevo régimen permanente, o pueden ser informadas por la carga. 4. Durante el transitorio, como mínimo un subsistema, o bien el convertidor principal o el AEP, debería operar en el lazo cerrado. Implementando un sistema en el lazo cerrado, preferiblemente el subsistema AEP por su ancho de banda elevado, se incrementa la robustez del sistema a los parásitos. Además, el AEP puede operar con cualquier tipo de corriente de carga. Las soluciones que funcionan en el lazo abierto suelen preformar el control de balance de carga con mínimo tiempo, así reducen la duración del transitorio y tienen un impacto menor a las pérdidas del sistema. Por otro lado, esas soluciones demuestran una alta sensibilidad a las tolerancias y parásitos de los componentes. 5. El AEP debería inyectar la corriente a la salida en una manera controlada, así se reduce el riesgo de unas corrientes elevadas y potencialmente peligrosas y se incrementa la robustez del sistema bajo las perturbaciones de la tensión de entrada. Ese problema suele ser relacionado con los sistemas donde el AEP es implementado como un convertidor auxiliar. El convertidor auxiliar es diseñado para una potencia baja, con lo cual, los dispositivos elegidos son de baja corriente/potencia. Si la corriente no es controlada, bajo un pico de tensión de entrada provocada por otro parte del sistema (por ejemplo, otro convertidor conectado al mismo bus), se puede llegar a un pico en la corriente auxiliar que puede causar la perturbación de tensión de salida e incluso el fallo de los dispositivos del convertidor auxiliar. Sin embargo, cuando la corriente es controlada, usando control del pico de corriente o control con histéresis, la corriente auxiliar tiene el control con prealimentación (feed-forward) de tensión de entrada y la corriente es definida y limitada. Por otro lado, si la solución utiliza el control de balance de carga, el sistema puede actuar de forma deficiente si la tensión de entrada tiene un valor diferente del nominal, provocando que el AEP inyecta/toma más/menos carga que necesitada. 6. Escalabilidad del sistema a convertidores multifase. Como ya ha sido comentado anteriormente, para las aplicaciones VRM por la corriente de carga elevada, el convertidor principal suele ser implementado como multifase para distribuir las perdidas entre las fases y bajar el estrés térmico de los dispositivos. Para asegurar el reparto de las corrientes, normalmente un control de modo corriente es usado. Las soluciones de SoA que usan VMC son limitadas a la implementación con solo una fase. Esta tesis propone un nuevo método de control del flujo de energía por el AEP y el convertidor principal. El concepto propuesto se basa en la inyección controlada de la corriente auxiliar al nodo de salida donde la amplitud de la corriente es n-1 veces mayor que la corriente del condensador de salida con las direcciones apropiadas. De esta manera, el AEP genera un condensador virtual cuya capacidad es n veces mayor que el condensador físico y reduce la impedancia de salida. Como el concepto propuesto reduce la impedancia de salida usando el AEP, el concepto es llamado Output Impedance Correction Circuit (OICC) concept. El concepto se desarrolla para un convertidor tipo reductor síncrono multifase con control modo de corriente CMC (incluyendo e implementación con una fase) y puede operar con la tensión de salida constante o con AVP. Además, el concepto es extendido a un convertidor de una fase con control modo de tensión VMC. Durante la operación, el control de tensión de salida de convertidor principal y control de corriente del subsistema OICC están siempre cerrados, incrementando la robustez a las tolerancias de componentes y a los parásitos del cirquito y permitiendo que el sistema se pueda enfrentar a cualquier tipo de la corriente de carga. Según el método de control propuesto, el sistema se puede encontrar en dos estados: durante el régimen permanente, el sistema se encuentra en el estado Idle y el subsistema OICC esta desactivado. Por otro lado, durante el transitorio, el sistema se encuentra en estado Activo y el subsistema OICC está activado para reducir la impedancia de salida. El cambio entre los estados se hace de forma autónoma: el sistema entra en el estado Activo observando la corriente de condensador de salida y vuelve al estado Idle cunado el nuevo régimen permanente es detectado, observando las variables del estado. La validación del concepto OICC es hecha aplicándolo a un convertidor tipo reductor síncrono con dos fases y de 30W cuyo condensador de salida tiene capacidad de 140μF, mientras el factor de multiplicación n es 15, generando en el estado Activo el condensador virtual de 2.1mF. El subsistema OICC es implementado como un convertidor tipo reductor síncrono con PCMC. Comparando el funcionamiento del convertidor con y sin el OICC, los resultados demuestran que se ha logrado una reducción de la desviación de tensión de salida con factor 12, tanto con funcionamiento básico como con funcionamiento AVP. Además, los resultados son comparados con un prototipo de referencia que tiene la misma etapa de potencia y un condensador de salida físico de 2.1mF. Los resultados demuestran que los dos sistemas tienen el mismo comportamiento dinámico. Más aun, se ha cuantificado el impacto en las pérdidas del sistema operando bajo una corriente de carga pulsante y bajo DVS. Se demuestra que el sistema con OICC mejora el rendimiento del sistema, considerando las pérdidas cuando el sistema trabaja con la carga pulsante y con DVS. Por lo último, el condensador de salida de sistema con OICC es mucho más pequeño que el condensador de salida del convertidor de referencia, con lo cual, por usar el concepto OICC, la densidad de energía se incrementa. En resumen, las contribuciones principales de la tesis son: • El concepto propuesto de Output Impedance Correction Circuit (OICC), • El control a nivel de sistema basado en el método usado para cambiar los estados de operación, • La implementación del subsistema OICC en lazo cerrado conjunto con la implementación del convertidor principal, • La cuantificación de las perdidas dinámicas bajo la carga pulsante y bajo la operación DVS, y • La robustez del sistema bajo la variación del condensador de salida y bajo los escalones de carga consecutiva. ABSTRACT Development of new technologies allows engineers to push the performance of the integrated circuits to its limits. New generations of processors, DSPs or FPGAs are able to process information with high speed and high consumption or to wait in low power mode with minimum possible consumption. This huge variation in power consumption and the short time needed to change from one level to another, affect the specifications of the Voltage Regulated Module (VRM) that supplies the IC. Furthermore, additional mandatory features, such as Adaptive Voltage Positioning (AVP) and Dynamic Voltage Scaling (DVS), impose opposite trends on the design of the VRM power stage. In order to cope with high load-step amplitudes, the output capacitor of the VRM power stage output filter is drastically oversized, penalizing power density and the efficiency during the DVS operation. Therefore, the ongoing research trend is directed to improve the dynamic response of the VRM while reducing the size of the output capacitor. The output capacitor reduction leads to a smaller cost and longer life-time of the system since the big bulk capacitors, usually implemented with OSCON capacitors, may not be needed to achieve the desired dynamic behavior. An additional advantage is that, by reducing the output capacitance, dynamic voltage scaling (DVS) can be performed faster and with smaller stress on the power stage, since the needed amount of charge to change the output voltage is smaller. The dynamic behavior of the system with a linear control (Voltage mode control, VMC, Peak Current Mode Control, PCMC,…) is limited by the converter switching frequency and filter size. The reduction of the output capacitor can be achieved by increasing the switching frequency of the converter, thus increasing the bandwidth of the system, and/or by applying advanced non-linear controls. Applying nonlinear control, the system variables get saturated in order to reach the new steady-state in a minimum time, thus the output filter, more specifically the output inductor current slew-rate, determines the output voltage response. Therefore, by reducing the output inductor value, the inductor current reaches faster the new steady state, so a smaller amount of charge is taken from the output capacitor during the transient. The drawback of this approach is that the system efficiency is penalized due to increased switching losses and RMS currents. In order to achieve both the output capacitor reduction and high system efficiency, while satisfying strict dynamic specifications, a Multiphase converter system is adopted as a standard for VRM applications. In order to ensure the current sharing among the phases, the multiphase converter is usually implemented with current mode control. In order to overcome the limitation imposed by the output filter, the second possibility to reduce the output capacitor is to apply Topologic modifications of the basic power stage topology in order to increase the slew-rate of the inductor current and, therefore, reduce the transient duration. Since the transient is reduced, smaller amount of charge is taken from the output capacitor under the same load current, thus, the output capacitor can be reduced to achieve the same output voltage deviation. The third possibility to reduce the output capacitor of the converter is to introduce an additional energy path (AEP) to compensate the charge unbalance of the output capacitor, consequently reducing the transient time and output voltage deviation. Doing so, during the steady-state operation the system has high efficiency because the main low-bandwidth converter is designed to operate at moderate switching frequency, to meet the static requirements, whereas the dynamic behavior during the transients is determined by the high-bandwidth auxiliary energy path. The auxiliary energy path can be implemented as a resistive path, as a Linear regulator, LR, or as a switching converter. The first two implementations provide higher bandwidth, at the expense of increasing losses during the transient. On the other hand, the switching converter implementation presents lower bandwidth, limited by the auxiliary converter switching frequency, though it produces smaller losses compared to the two previous implementations. Depending on the application, the implementation and the control strategy of the system, there is a variety of proposed solutions in the State-of-the-Art (SoA), having different features where one solution offers some advantages over the others, but also some disadvantages. In general, an ideal additional energy path system should have the following features: 1. The impact on the system losses should be minimal. During its operation, the AEP generates additional losses, thus ideally, the AEP should operate for a short period of time, only when the transient is occurring; the other option is to have the AEP constantly on, but due to the inductor current ripple compensation at the output, unnecessary losses are generated. 2. The AEP should be activated nearly instantaneously to prevent bigger output voltage deviation. To achieve near instantaneous activation, the converter system can be informed by the load prior to the load-step or the system can observe the output capacitor current, which is the first system state variable that reacts on the load current perturbation. In this manner, the AEP is turned on with near zero output voltage error, providing smaller output voltage deviation. 3. The AEP should be deactivated once the new steady state is reached to avoid additional settling transients. Most of the SoA solutions estimate duration of the transient which may cause additional transient if the estimation is not performed correctly (e.g. if the main converter inductor current has higher or lower value than needed, the slow regulator of the main converter needs to compensate the difference after the AEP is deactivated). Other SoA solutions are observing state variables, ensuring that the system reaches the new steady state or they are informed by the load. 4. During the transient, at least one subsystem, either the main converter or the AEP, should be in closed-loop. Implementing a closed loop system, preferably the AEP subsystem, due its higher bandwidth, increases the robustness under system tolerances and circuit parasitic. In addition, the AEP can operate with any type of load. The solutions that operate in open loop usually perform minimum time charge balance control, thus reducing the transient length and minimizing the impact on the losses, however they are very sensitive to tolerances and parasitics. 5. The AEP should inject current at the output in a controlled manner, thus reducing the risk of high and potentially damaging currents and increasing robustness on the input voltage deviation. This issue is mainly related to the systems where AEP is implemented as auxiliary converter. The auxiliary converter is designed for small power and, as such, the MOSFETs are rated for small power/currents. If the current is not controlled, due to the some unpredicted spike in input voltage caused by some other part of the system (e.g. different converter), it may lead to a current spike in auxiliary current which will cause the perturbation of the output voltage and even failure of the switching components of auxiliary converter. In the case when the current is controlled, using peak CMC or Hysteretic Window CMC, the auxiliary converter has inherent feed-forwarding of the input voltage in current control and the current is defined and limited. Furthermore, if the solution employs charge balance control, the system may perform poorly if the input voltage has different value than the nominal, causing that AEP injects/extracts more/less charge than needed. 6. Scalability of the system to multiphase converters. As commented previously, in VRM applications, due to the high load currents, the main converters are implemented as multiphase to redistribute losses among the modules, lowering temperature stress of the components. To ensure the current sharing, usually a Current Mode Control (CMC) is employed. The SoA solutions that are implemented with VMC are limited to a single stage implementation. This thesis proposes a novel control method of the energy flow through the AEP and the main converter system. The proposed concept relays on a controlled injection of the auxiliary current at the output node where the instantaneous current value is n-1 times bigger than the output capacitor current with appropriate directions. Doing so, the AEP creates an equivalent n times bigger virtual capacitor at the output, thus reducing the output impedance. Due to the fact that the proposed concept reduces the output impedance using the AEP, it has been named the Output Impedance Correction Circuit (OICC) concept. The concept is developed for a multiphase CMC synchronous buck converter (including a single phase implementation), operating with a constant output voltage and with AVP feature. Further, it is extended to a single phase VMC synchronous buck converter. During the operation, the main converter voltage loop and the OICC subsystem capacitor current loop is constantly closed, increasing the robustness under system tolerances and circuit parasitic and allowing the system to operate with any load-current shape or pattern. According to the proposed control method, the system operates in two states: during the steady-state the system is in the Idle state and the OICC subsystem is deactivated, while during the load-step transient the system is in the Active state and the OICC subsystem is activated in order to reduce the output impedance. The state changes are performed autonomously: the system enters in the Active state by observing the output capacitor current and it returns back to the Idle state when the steady-state operation is detected by observing the state variables. The validation of the OICC concept has been done by applying it to a 30W two phase synchronous buck converter with 140μF output capacitor and with the multiplication factor n equal to 15, generating during the Active state equivalent output capacitor of 2.1mF. The OICC subsystem is implemented as single phase PCMC synchronous buck converter. Comparing the converter operation with and without the OICC the results demonstrate that the 12 times reduction of the output voltage deviation is achieved, for both basic operation and for the AVP operation. Furthermore, the results have been compared to a reference prototype which has the same power stage and a fiscal output capacitor of 2.1mF. The results show that the two systems have the same dynamic behavior. Moreover, an impact on the system losses under the pulsating load and DVS operation has been quantified and it has been demonstrated that the OICC system has improved the system efficiency, considering the losses when the system operates with the pulsating load and the DVS operation. Lastly, the output capacitor of the OICC system is much smaller than the reference design output capacitor, therefore, by applying the OICC concept the power density can be increased. In summary, the main contributions of the thesis are: • The proposed Output Impedance Correction Circuit (OICC) concept, • The system level control based on the used approach to change the states of operation, • The OICC subsystem closed-loop implementation, together with the main converter implementation, • The dynamic losses under the pulsating load and the DVS operation quantification, and • The system robustness on the capacitor impedance variation and consecutive load-steps.
Resumo:
Learning is widely thought to result from altered potency of synapses within the neural pathways that mediate the learned behavior. Support for this belief, which pervades current physiological and computational thinking, comes especially from the analysis of cases of simple learning in invertebrates. Here, evidence is presented that in one such case, habituation of crayfish escape, the learning is more due to onset of tonic descending inhibition than to the intrinsic depression of circuit synapses to which it was previously attributed. Thus, the altered performance seems to depend at least as much on events in higher centers as on local plasticity.