An automated failure mode and effect analysis based on high-level design specificication with behavior trees

Formal methods have significant benefits for developing safety critical systems, in that they allow for correctness proofs, model checking safety and liveness properties, deadlock checking, etc. However, formal methods do not scale very well and demand specialist skills, when developing real-world systems. For these reasons, development and analysis of large-scale safety critical systems will require effective integration of formal and informal methods. In this paper, we use such an integrative approach to automate Failure Modes and Effects Analysis (FMEA), a widely used system safety analysis technique, using a high-level graphical modelling notation (Behavior Trees) and model checking. We inject component failure modes into the Behavior Trees and translate the resulting Behavior Trees to SAL code. This enables us to model check if the system in the presence of these faults satisfies its safety properties, specified by temporal logic formulas. The benefit of this process is tool support that automates the tedious and error-prone aspects of FMEA.

Comparison of high level FPGA hardware design for solving tri-diagonal linear systems

Reconfigurable computing devices can increase the performance of compute intensive algorithms by implementing application specific co-processor architectures. The power cost for this performance gain is often an order of magnitude less than that of modern CPUs and GPUs. Exploiting the potential of reconfigurable devices such as Field-Programmable Gate Arrays (FPGAs) is typically a complex and tedious hardware engineering task. Re- cently the major FPGA vendors (Altera, and Xilinx) have released their own high-level design tools, which have great potential for rapid development of FPGA based custom accelerators. In this paper, we will evaluate Altera’s OpenCL Software Development Kit, and Xilinx’s Vivado High Level Sythesis tool. These tools will be compared for their per- formance, logic utilisation, and ease of development for the test case of a Tri-diagonal linear system solver.

H-DBUG: A High-level Debugging Framework for Protocol Verification using Assertions

The success of an ABV IP depends highly on the associated debugging environment. An efficient debugging environment helps the user to find out the exact location of the failure. Moreover, it provides information to the user in a refined detail of abstraction and permit adequate interaction. It has also been realized that adequate visualization support helps in tracking the behavioral aspects of the Design Under Test (DUT). Currently, the debugging tools provide information in the signal level and do not provide any information about the high-level behavior of the DUT. We present a debugging framework that takes the design specification, assertions and the user intent in a simple format and provides detailed information by processing the design trace on-line, or off-line. We also present a visualization framework to ease the debugging procedure. We have experimented with industrial standard on-chip bus protocols that ensure that this utility can be incorporated successfully in the present functional verification flow.

Design, specification, and synthesis of aircraft electric power systems control logic

Cyber-physical systems integrate computation, networking, and physical processes. Substantial research challenges exist in the design and verification of such large-scale, distributed sensing, ac- tuation, and control systems. Rapidly improving technology and recent advances in control theory, networked systems, and computer science give us the opportunity to drastically improve our approach to integrated flow of information and cooperative behavior. Current systems rely on text-based spec- ifications and manual design. Using new technology advances, we can create easier, more efficient, and cheaper ways of developing these control systems. This thesis will focus on design considera- tions for system topologies, ways to formally and automatically specify requirements, and methods to synthesize reactive control protocols, all within the context of an aircraft electric power system as a representative application area.

This thesis consists of three complementary parts: synthesis, specification, and design. The first section focuses on the synthesis of central and distributed reactive controllers for an aircraft elec- tric power system. This approach incorporates methodologies from computer science and control. The resulting controllers are correct by construction with respect to system requirements, which are formulated using the specification language of linear temporal logic (LTL). The second section addresses how to formally specify requirements and introduces a domain-specific language for electric power systems. A software tool automatically converts high-level requirements into LTL and synthesizes a controller.

The final sections focus on design space exploration. A design methodology is proposed that uses mixed-integer linear programming to obtain candidate topologies, which are then used to synthesize controllers. The discrete-time control logic is then verified in real-time by two methods: hardware and simulation. Finally, the problem of partial observability and dynamic state estimation is ex- plored. Given a set placement of sensors on an electric power system, measurements from these sensors can be used in conjunction with control logic to infer the state of the system.

Improvement and evaluation of the MS2SV for mixed systems design described in abstraction high level

This paper presents an important improvement of the MS2SV tool. The MS2SV performs the translation of mixed systems developed in MATLAB / Simulink for a structural or behavioral description in VHDL-AMS. Previously, the MS2SV translated only models of the LIB MS2SV library. This improvement allows designer to create your own library to translation. As case study was used a rudder controller employed in an unmanned aerial vehicle. For comparison with the original model the VHDL-AMS code obtained by the translation was simulated in SystemVision environment. The results proved the efficiency of the tool using the translation improvement proposed in this paper.

EMI issues in high power and high level diode-clamped converters

Planar busbar is a good candidate to reduce interconnection inductance in high power inverters compared with cables. However, power switching components with fast switching combined with hard switched-converters produce high di/dt during turn off time and busbar stray inductance then becomes an important issue which creates overvoltage. It is necessary to keep the busbar stray inductance as low as possible to decrease overvoltage and Electromagnetic Interference (EMI) noise. In this paper, the effect of different transient current loops on busbar physical structure of the high-voltage high-level diode-clamped converters will be highlighted. Design considerations of proper planar busbar will also be presented to optimise the overall design of diode-clamped converters.

Teaching games level design using the StarCraft II editor

Level design is often characterised as “where the rubber hits the road” in game development. It is a core area of games design, alongside design of game rules and narrative. However, there is a lack of literature dedicated to documenting teaching games design, let alone the more specialised topic of level design. Furthermore, there is a lack of formal frameworks for best practice in level design, as professional game developers often rely on intuition and previous experience. As a result, there is little for games design teachers to draw on when presented with the opportunity to teach a level design unit. In this paper, we discuss the design and implementation of a games level design unit in which students use the StarCraft II Galaxy Editor. We report on two cycles of an action research project, reflecting upon our experiences with respect to student feedback and peer review, and outlining our plans for improving the unit in years to come.

High-level expression of Rhodotorula gracilis d-amino acid oxidase in Pichia pastoris

By combining gene design and heterologous over-expression of Rhodotorula gracilis D-amino acid oxidase (RgDAO) in Pichia pastoris, enzyme production was enhanced by one order of magnitude compared to literature benchmarks, giving 350 kUnits/l of fed-batch bioreactor culture with a productivity of 3.1 kUnits/l h. P. pastoris cells permeabilized by freeze-drying and incubation in 2-propanol (10% v/v) produce a highly active (1.6 kUnits/g dry matter) and stable oxidase preparation. Critical bottlenecks in the development of an RgDAO catalyst for industrial applications have been eliminated.

Hybrid address spaces: A methodology for implementing scalable high-level programming models on non-coherent many-core architectures

This paper introduces hybrid address spaces as a fundamental design methodology for implementing scalable runtime systems on many-core architectures without hardware support for cache coherence. We use hybrid address spaces for an implementation of MapReduce, a programming model for large-scale data processing, and the implementation of a remote memory access (RMA) model. Both implementations are available on the Intel SCC and are portable to similar architectures. We present the design and implementation of HyMR, a MapReduce runtime system whereby different stages and the synchronization operations between them alternate between a distributed memory address space and a shared memory address space, to improve performance and scalability. We compare HyMR to a reference implementation and we find that HyMR improves performance by a factor of 1.71× over a set of representative MapReduce benchmarks. We also compare HyMR with Phoenix++, a state-of-art implementation for systems with hardware-managed cache coherence in terms of scalability and sustained to peak data processing bandwidth, where HyMR demon- strates improvements of a factor of 3.1× and 3.2× respectively. We further evaluate our hybrid remote memory access (HyRMA) programming model and assess its performance to be superior of that of message passing.

Role of Automated Open Source Systems in the Intelligence Analysis of a High-Level Domain Expert

Performance-Driven Microfabrication-Oriented Methodology for MEMS Conceptual Design with Application in Microfluidic Device Design

Performance and manufacturability are two important issues that must be taken into account during MEMS design. Existing MEMS design models or systems follow a process-driven design paradigm, that is, design starts from the specification of process sequence or the customization of foundry-ready process template. There has been essentially no methodology or model that supports generic, high-level design synthesis for MEMS conceptual design. As a result, there lacks a basis for specifying the initial process sequences. To address this problem, this paper proposes a performance-driven, microfabrication-oriented methodology for MEMS conceptual design. A unified behaviour representation method is proposed which incorporates information of both physical interactions and chemical/biological/other reactions. Based on this method, a behavioural process based design synthesis model is proposed, which exploits multidisciplinary phenomena for design solutions, including both the structural components and their configuration for the MEMS device, as well as the necessary substances for the chemical/biological/other reactions. The model supports both forward and backward synthetic search for suitable phenomena. To ensure manufacturability, a strategy of using microfabrication-oriented phenomena as design knowledge is proposed, where the phenomena are developed from existing MEMS devices that have associated MEMS-specific microfabrication processes or foundry-ready process templates. To test the applicability of the proposed methodology, the paper also studies microfluidic device design and uses a micro-pump design for the case study.