Correlation modeling for a distributed scalable video codec based on the HEVC standard

The growing heterogeneity of networks, devices and consumption conditions asks for flexible and adaptive video coding solutions. The compression power of the HEVC standard and the benefits of the distributed video coding paradigm allow designing novel scalable coding solutions with improved error robustness and low encoding complexity while still achieving competitive compression efficiency. In this context, this paper proposes a novel scalable video coding scheme using a HEVC Intra compliant base layer and a distributed coding approach in the enhancement layers (EL). This design inherits the HEVC compression efficiency while providing low encoding complexity at the enhancement layers. The temporal correlation is exploited at the decoder to create the EL side information (SI) residue, an estimation of the original residue. The EL encoder sends only the data that cannot be inferred at the decoder, thus exploiting the correlation between the original and SI residues; however, this correlation must be characterized with an accurate correlation model to obtain coding efficiency improvements. Therefore, this paper proposes a correlation modeling solution to be used at both encoder and decoder, without requiring a feedback channel. Experiments results confirm that the proposed scalable coding scheme has lower encoding complexity and provides BD-Rate savings up to 3.43% in comparison with the HEVC Intra scalable extension under development. © 2014 IEEE.

Integración de RVC-HEVC y OpenHEVC sobre la plataforma MultiDSP C6678

Este proyecto se basa en la integración de funciones optimizadas de OpenHEVC en el códec Reconfigurable Video Coding (RVC) - High Efficiency Video Coding (HEVC). RVC es un framework capaz de generar automáticamente el código que implementa cualquier estándar de video mediante el uso de librerías. Estas librerías contienen la definición de bloques funcionales de los que se componen los distintos estándares de video a implementar. Sin embargo, como desventaja a la facilidad de creación de estándares utilizando este framework, las librerías que utiliza no se encuentran optimizadas. Por ello se pretende que el códec RVC-HEVC sea capaz de realizar llamadas a funciones optimizadas, que para el estudio éstas se encontrarán en la librería OpenHEVC. Por otro lado, estos codificadores de video se pueden encontrar implementados tanto en PCs como en sistemas embebidos. Los Digital Signal Processors (DSPs) son unas plataformas especializadas en el procesamiento digital, teniendo una alta velocidad en el cómputo de operaciones matemáticas. Por ello, para este proyecto se integrará RVC-HEVC con las llamadas a OpenHEVC en una plataforma DSP como la TMS320C6678. Una vez completa la integración se efectuan medidas de eficiencia para ver cómo las llamadas a funciones optimizadas mejoran la velocidad en la decodificación de imágenes. ABSTRACT. This project is based in the integration of optimized functions from OpenHEVC in the RVC-HEVC (Reconfigurable Video Coding- High Efficiency Video Coding) codec. RVC is a framework capable of generating automatically any type of video standard with the use of libraries. Inside these libraries there are the definitions of the functional blocks which make up the different standards, in which for the case of study will be the HEVC standard. Nevertheless, as a downside for the simplicity in producing standards with the RVC tool, these libraries are not optimized. Thus, one of the goals for the project will be to make the RVC-HEVC call optimized functions, in which in this case they will be inside the OpenHEVC library. On the other hand, these video encoders can be implemented both in PCs and embedded systems. The DSPs (Digital Signal Processors) are platforms specialized in digital processing, being able to compute mathematical operations in a short period of time. Consequently, for this project the integration of the RVC-HEVC with calls to the OpenHEVC library will be done in a DSP platform such as a TMS320C6678. Once completed the integration, performance measures will be carried out to evaluate the improvement in the decoding speed obtained when optimized functions are used by the RVC-HEVC.

Methodologies for implement video decoders over multiprocessor platforms

The latest video coding standards developed, like HEVC (High Efficiency Video Coding, approved in January 2013), require for their implementation the use of devices able to support a high computational load. Considering that currently it is not enough the usage of one unique Digital Signal Processor (DSP), multicore devices have appeared recently in the market. However, due to its novelty, the working methodology that allows produce solutions for these configurations is in a very initial state, since currently the most part of the work needs to be performed manually. In consequence, the objective set consists on finding methodologies that ease this process. The study has been focused on extend a methodology, under development, for the generation of solutions for PCs and embedded systems. During this study, the standards RVC (Reconfigurable Video Coding) and HEVC have been employed, as well as DSPs of the Texas Instruments company. In its development, it has been tried to address all the factors that influence both the development and deployment of these new implementations of video decoders, ranging from tools up to aspects of the partitioning of algorithms, without this can cause a drop in application performance. The results of this study are the description of the employed methodology, the characterization of the software migration process and performance measurements for the HEVC standard in an RVC-based implementation. RESUMEN Los estándares de codificación de vídeo desarrollados más recientemente, como HEVC (High Efficiency Video Coding, aprobado en enero de 2013), requieren para su implementación el uso de dispositivos capaces de soportar una elevada carga computacional. Teniendo en cuenta que actualmente no es suficiente con utilizar un único Procesador Digital de Señal (DSP), han aparecido recientemente dispositivos multinúcleo en el mercado. Sin embargo, debido a su novedad, la metodología de trabajo que permite elaborar soluciones para tales configuraciones se encuentra en un estado muy inicial, ya que actualmente la mayor parte del trabajo debe realizarse manualmente. En consecuencia, el objetivo marcado consiste en encontrar metodologías que faciliten este proceso. El estudio se ha centrado en extender una metodología, en desarrollo, para la generación de soluciones para PC y sistemas empotrados. Durante dicho estudio se han empleado los estándares RVC (Reconfigurable Video Coding) y HEVC, así como DSPs de la compañía Texas Instruments. En su desarrollo se ha tratado de atender a todos los factores que influyen tanto en el desarrollo como en la puesta en marcha de estas nuevas implementaciones de descodificadores de vídeo; abarcando desde las herramientas a utilizar hasta aspectos del particionado de los algoritmos, sin que por ello se produzca una reducción en el rendimiento de las aplicaciones. Los resultados de este estudio son una descripción de la metodología empleada, la caracterización del proceso de migración de software, y medidas de rendimiento para el estándar HEVC en una implementación basada en RVC.

High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs

A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps).

Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e. g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 x 4,320 at 30 fps) in real time.

Caracterización de un descodificador HEVC ejecutándose en un DSP

HEVC es el nuevo estándar de codificación de vídeo que está siendo desarrollado conjuntamente por las organizaciones ITU-T Video Coding Experts Group (VCEG) e ISO/IEC Moving Picture Experts Group (MPEG). Su objetivo principal es mejorar la compresión de vídeo, en relación a los actuales estándares. Es común hoy en día, debido a su flexibilidad para aplicaciones de bajo consumo, diseñar sistemas de descodificación de vídeo basados en un procesador digital de señal (DSP). En la mayoría de las veces, los diseños parten de un código creado para ser ejecutado en un ordenador personal y posteriormente se optimizan para tecnología DSP. El objetivo principal de este proyecto es caracterizar el rendimiento de un sistema basado en DSP que ejecute el código de un descodificador de video HEVC. ABSTRACT. HEVC is a new video coding standard which is being developed by both ITU-T Video Coding Experts Group (VCEG) and ISO/IEC Moving Picture Experts Group (MPEG). Its main goal is to improve video compression, compared with the actual standards. It is common practice, because of the flexibility in low power applications, to design video decoding systems using digital signal processors (DSP). Most of the time, these designs start with a code suitable to be executed in personal computers and then it is optimized forDSP technology. The main goal in this final degree project is to characterize the performance of a DSP based system executing an HEVC video decoder.

Diseño y banco de test VHDL de un procesador que realice la ICT para HEVC

Se va a realizar un estudio de la codificación de imágenes sobre el estándar HEVC (high-effiency video coding). El proyecto se va a centrar en el codificador híbrido, más concretamente sobre la aplicación de la transformada inversa del coseno que se realiza tanto en codificador como en el descodificador. La necesidad de codificar vídeo surge por la aparición de la secuencia de imágenes como señales digitales. El problema principal que tiene el vídeo es la cantidad de bits que aparecen al realizar la codificación. Como consecuencia del aumento de la calidad de las imágenes, se produce un crecimiento exponencial de la cantidad de información a codificar. La utilización de las transformadas al procesamiento digital de imágenes ha aumentado a lo largo de los años. La transformada inversa del coseno se ha convertido en el método más utilizado en el campo de la codificación de imágenes y video. Las ventajas de la transformada inversa del coseno permiten obtener altos índices de compresión a muy bajo coste. La teoría de las transformadas ha mejorado el procesamiento de imágenes. En la codificación por transformada, una imagen se divide en bloques y se identifica cada imagen a un conjunto de coeficientes. Esta codificación se aprovecha de las dependencias estadísticas de las imágenes para reducir la cantidad de datos. El proyecto realiza un estudio de la evolución a lo largo de los años de los distintos estándares de codificación de video. Se analiza el codificador híbrido con más profundidad así como el estándar HEVC. El objetivo final que busca este proyecto fin de carrera es la realización del núcleo de un procesador específico para la ejecución de la transformada inversa del coseno en un descodificador de vídeo compatible con el estándar HEVC. Es objetivo se logra siguiendo una serie de etapas, en las que se va añadiendo requisitos. Este sistema permite al diseñador hardware ir adquiriendo una experiencia y un conocimiento más profundo de la arquitectura final. ABSTRACT. A study about the codification of images based on the standard HEVC (high-efficiency video coding) will be developed. The project will be based on the hybrid encoder, in particular, on the application of the inverse cosine transform, which is used for the encoder as well as for the decoder. The necessity of encoding video arises because of the appearance of the sequence of images as digital signals. The main problem that video faces is the amount of bits that appear when making the codification. As a consequence of the increase of the quality of the images, an exponential growth on the quantity of information that should be encoded happens. The usage of transforms to the digital processing of images has increased along the years. The inverse cosine transform has become the most used method in the field of codification of images and video. The advantages of the inverse cosine transform allow to obtain high levels of comprehension at a very low price. The theory of the transforms has improved the processing of images. In the codification by transform, an image is divided in blocks and each image is identified to a set of coefficients. This codification takes advantage of the statistic dependence of the images to reduce the amount of data. The project develops a study of the evolution along the years of the different standards in video codification. In addition, the hybrid encoder and the standard HEVC are analyzed more in depth. The final objective of this end of degree project is the realization of the nucleus from a specific processor for the execution of the inverse cosine transform in a decoder of video that is compatible with the standard HEVC. This objective is reached following a series of stages, in which requirements are added. This system allows the hardware designer to acquire a deeper experience and knowledge of the final architecture.

Contributions to HEVC Prediction for Medical Image Compression

Medical imaging technology and applications are continuously evolving, dealing with images of increasing spatial and temporal resolutions, which allow easier and more accurate medical diagnosis. However, this increase in resolution demands a growing amount of data to be stored and transmitted. Despite the high coding efficiency achieved by the most recent image and video coding standards in lossy compression, they are not well suited for quality-critical medical image compression where either near-lossless or lossless coding is required. In this dissertation, two different approaches to improve lossless coding of volumetric medical images, such as Magnetic Resonance and Computed Tomography, were studied and implemented using the latest standard High Efficiency Video Encoder (HEVC). In a first approach, the use of geometric transformations to perform inter-slice prediction was investigated. For the second approach, a pixel-wise prediction technique, based on Least-Squares prediction, that exploits inter-slice redundancy was proposed to extend the current HEVC lossless tools. Experimental results show a bitrate reduction between 45% and 49%, when compared with DICOM recommended encoders, and 13.7% when compared with standard HEVC.

A Feasibility Study Of Fricke Dosimetry As An Absorbed Dose To Water Standard For 192ir Hdr Sources.

High dose rate brachytherapy (HDR) using 192Ir sources is well accepted as an important treatment option and thus requires an accurate dosimetry standard. However, a dosimetry standard for the direct measurement of the absolute dose to water for this particular source type is currently not available. An improved standard for the absorbed dose to water based on Fricke dosimetry of HDR 192Ir brachytherapy sources is presented in this study. The main goal of this paper is to demonstrate the potential usefulness of the Fricke dosimetry technique for the standardization of the quantity absorbed dose to water for 192Ir sources. A molded, double-walled, spherical vessel for water containing the Fricke solution was constructed based on the Fricke system. The authors measured the absorbed dose to water and compared it with the doses calculated using the AAPM TG-43 report. The overall combined uncertainty associated with the measurements using Fricke dosimetry was 1.4% for k = 1, which is better than the uncertainties reported in previous studies. These results are promising; hence, the use of Fricke dosimetry to measure the absorbed dose to water as a standard for HDR 192Ir may be possible in the future.

Sensitivity and specificity of machine learning classifiers for glaucoma diagnosis using Spectral Domain OCT and standard automated perimetry

PURPOSE: To evaluate the sensitivity and specificity of machine learning classifiers (MLCs) for glaucoma diagnosis using Spectral Domain OCT (SD-OCT) and standard automated perimetry (SAP). METHODS: Observational cross-sectional study. Sixty two glaucoma patients and 48 healthy individuals were included. All patients underwent a complete ophthalmologic examination, achromatic standard automated perimetry (SAP) and retinal nerve fiber layer (RNFL) imaging with SD-OCT (Cirrus HD-OCT; Carl Zeiss Meditec Inc., Dublin, California). Receiver operating characteristic (ROC) curves were obtained for all SD-OCT parameters and global indices of SAP. Subsequently, the following MLCs were tested using parameters from the SD-OCT and SAP: Bagging (BAG), Naive-Bayes (NB), Multilayer Perceptron (MLP), Radial Basis Function (RBF), Random Forest (RAN), Ensemble Selection (ENS), Classification Tree (CTREE), Ada Boost M1(ADA),Support Vector Machine Linear (SVML) and Support Vector Machine Gaussian (SVMG). Areas under the receiver operating characteristic curves (aROC) obtained for isolated SAP and OCT parameters were compared with MLCs using OCT+SAP data. RESULTS: Combining OCT and SAP data, MLCs' aROCs varied from 0.777(CTREE) to 0.946 (RAN).The best OCT+SAP aROC obtained with RAN (0.946) was significantly larger the best single OCT parameter (p<0.05), but was not significantly different from the aROC obtained with the best single SAP parameter (p=0.19). CONCLUSION: Machine learning classifiers trained on OCT and SAP data can successfully discriminate between healthy and glaucomatous eyes. The combination of OCT and SAP measurements improved the diagnostic accuracy compared with OCT data alone.

Free expanding cloud of cold atoms as an atomic standard: Ramsey fringes contrast

A compact frequency standard based on an expanding cold (133)CS cloud is under development in our laboratory. In a first experiment, Cs cold atoms were prepared by a magneto-optical trap in a vapor cell, and a microwave antenna was used to transmit the radiation for the clock transition. The signal obtained from fluorescence of the expanding cold atoms cloud is used to lock a microwave chain. In this way the overall system stability is evaluated. A theoretical model based on a two-level system interacting with the two microwave pulses enables interpretation for the observed features, especially the poor Ramsey fringes contrast. (C) 2008 Optical Society of America.

Duality linking standard and tachyon scalar field cosmologies

In this work we investigate the duality linking standard and tachyon scalar field homogeneous and isotropic cosmologies in N + 1 dimensions. We determine the transformation between standard and tachyon scalar fields and between their associated potentials, corresponding to the same background evolution. We show that, in general, the duality is broken at a perturbative level, when deviations from a homogeneous and isotropic background are taken into account. However, we find that for slow-rolling fields the duality is still preserved at a linear level. We illustrate our results with specific examples of cosmological relevance, where the correspondence between scalar and tachyon scalar field models can be calculated explicitly.

Quasinormal modes of brane-localized standard model fields in Gauss-Bonnet theory

We study the massless scalar, Dirac, and electromagnetic fields propagating on a 4D-brane, which is embedded in higher-dimensional Gauss-Bonnet space-time. We calculate, in the time domain, the fundamental quasinormal modes of a spherically symmetric black hole for such fields. Using WKB approximation we study quasinormal modes in the large multipole limit. We observe also a universal behavior, independent on a field and value of the Gauss-Bonnet parameter, at an asymptotically late time.

Sequential injection analysis implementing multiple standard additions for As speciation by liquid chromatography and atomic fluorescence spectrometry (SIA-HPLC-AFS)

An analytical procedure for multiple standard additions of arsenic species using sequential injection analysis (SIA) is proposed for their quantification in seafood extracts. SIA presented flexibility for generating multiple specie standards at the ng mL(-1) concentration level by adding different volumes of As(III), As(V), monomethylarsonic (MMA) and dimethylarsinic (DMA) to the sample. The mixed sample plus standard solutions were delivered from SIA to fill the HPLC injection loop. Subsequently, As species were separated by HPLC and analyzed by atomic fluorescence spectrometry (AFS). The proposed system comprised two independently controlled modules, with the HPLC loop acting as the intermediary device. The analytical frequency was enhanced by combining the actions of both modules. While the added sample was flowing through the chromatographic column towards the detection system, the SIA program started performing the standard additions to another sample. The proposed method was applied to spoiled seafood extracts. Detection limits based on 3 sigma for As(III), As(V), MMA and DMA were 0.023, 0.39, 0.45 and 1.0 ng mL(-1), respectively. (C) 2011 Elsevier B.V. All rights reserved.