Development and reliability of a direct access sensor using flip chip on flex technology with anisotropic conductive adhesive

Technological developments in biomedical microsystems are opening up new opportunities to improve healthcare procedures. Swallowable diagnostic sensing capsules are an example of these. In none of the diagnostic sensing capsules, is the sensor’s first level packaging achieved via Flip Chip Over Hole (FCOH) method using Anisotropic Conductive Adhesive (ACA). In a capsule application with direct access sensor (DAS), ACA not only provides the electrical interconnection but simultaneously seals the interconnect area and the underlying electronics. The development showed that the ACA FCOH was a viable option for the DAS interconnection. Adequate adhesive formed a strong joint that withstood a shear stress of 120N/mm2 and a compressive stress of 6N required to secure the final sensor assembly in place before encapsulation. Electrical characterization of the ACA joint in a fluid environment showed that the ACA was saturated with moisture and that the ions in the solution actively contributed to the leakage current, characterized by the varying rate of change of conductance. Long term hygrothermal aging of the ACA joint showed that a thermal strain of 0.004 and a hygroscopic strain of 0.0052 were present and resulted in a fatigue like process. In-vitro tests showed that high temperature and acidity had a deleterious effect of the ACA and its joint. It also showed that the ACA contact joints positioned at around or over 1mm would survive the gastrointestinal (GI) fluids and would be able to provide a reliable contact during the entire 72hr of the GI transit time. A final capsule demonstrator was achieved by successfully integrating the DAS, the battery and the final foldable circuitry into a glycerine capsule. Final capsule soak tests suggested that the silicone encapsulated system could survive the 72hr gut transition.

Effect of solder volume on joint shape with variable chip-to-board contact pad ratio

The objective of this paper is to investigate the effect of the pad size ratio between the chip and board end of a solder joint on the shape of that solder joint in combination with the solder volume available. The shape of the solder joint is correlated to its reliability and thus of importance. For low density chip bond pad applications Flip Chip (FC) manufacturing costs can be kept down by using larger size board pads suitable for solder application. By using “Surface Evolver” software package the solder joint shapes associated with different size/shape solder preforms and chip/board pad ratios are predicted. In this case a so called Flip-Chip Over Hole (FCOH) assembly format has been used. Assembly trials involved the deposition of lead-free 99.3Sn0.7Cu solder on the board side, followed by reflow, an underfill process and back die encapsulation. During the assembly work pad off-sets occurred that have been taken into account for the Surface Evolver solder joint shape prediction and accurately matched the real assembly. Overall, good correlation was found between the simulated solder joint shape and the actual fabricated solder joint shapes. Solder preforms were found to exhibit better control over the solder volume. Reflow simulation of commercially available solder preform volumes suggests that for a fixed stand-off height and chip-board pad ratio, the solder volume value and the surface tension determines the shape of the joint.

System packaging & integration for a swallowable capsule using a direct access sensor

Technological developments in biomedical microsystems are opening up new opportunities to improve healthcare procedures. Swallowable diagnostic capsules are an example of this. In this paper, a diagnostic capsule technology is described based on direct-access sensing of the Gastro Intestinal (GI) fluids throughout the GI tract. The objective of this paper is two-fold: i) develop a packaging method for a direct access sensor, ii) develop an encapsulation method to protect the system electronics. The integrity of the interconnection after sensor packaging and encapsulation is correlated to its reliability and thus of importance. The zero level packaging of the sensor was achieved by using a so called Flip Chip Over Hole (FCOH) method. This allowed the fluidic sensing media to interface with the sensor, while the rest of the chip including the electrical connections can be insulated effectively. Initial tests using Anisotropic Conductive Adhesive (ACA) interconnect for the FCOH demonstrated good electrical connections and functionality of the sensor chip. Also a preliminary encapsulation trial of the flip chipped sensor on a flexible test substrate has been carried out and showed that silicone encapsulation of the system is a viable option.

Material properties, geometry and their effect on the fatigue life of two flip-chip models

This paper describes how modeling technology has been used in providing fatigue life time data of two flip-chip models. Full-scale three-dimensional modeling of flip-chips under cyclic thermal loading has been combined with solder joint stand-off height prediction to analyze the stress and strain conditions in the two models. The Coffin-Manson empirical relationship is employed to predict the fatigue life times of the solder interconnects. In order to help designers in selecting the underfill material and the printed circuit board, the Young's modulus and the coefficient of thermal expansion of the underfill, as well as the thickness of the printed circuit boards are treated as variable parameters. Fatigue life times are therefore calculated over a range of these material and geometry parameters. In this paper we will also describe how the use of micro-via technology may affect fatigue life

No-flow underfill flip chip assembly–an experimental and modeling analysis

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal–mechanical fatigue life of flip chips with no-flow underfill.

A modelling and experimental analysis of the no-flow underfill process for flip-chip assembly

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfills as the application and curing of this type of underfill can be undertaken before and during the reflow process - adding high volume throughput. Adopting a no-flow underfill process may result in underfill entrapment between solder and fluid, voiding in the underfill, a possible delamination between underfill and surrounding surfaces. The magnitude of these phenomena may adversely affect the reliability of the assembly in terms of solder joint thermal fatigue. This paper presents both an experimental and mdeling analysis investigating the reliabity of a flip-chip component and how the magnitude of underfill entrapment may affect thermal-mechanical fatigue life.

Role of bonding time and temperature on the physical properties of coupled anisotropic conductive–nonconductive adhesive film for flip chip on glass technology

Using thermosetting epoxy based conductive adhesive films for the flip chip interconnect possess a great deal of attractions to the electronics manufacturing industries due to the ever increasing demands for miniaturized electronic products. Adhesive manufacturers have taken many attempts over the last decade to produce a number of types of adhesives and the coupled anisotropic conductive-nonconductive adhesive film is one of them. The successful formation of the flip chip interconnection using this particular type of adhesive depends on, among factors, how the physical properties of the adhesive changes during the bonding process. Experimental measurements of the temperature in the adhesive have revealed that the temperature becomes very close to the required maximum bonding temperature within the first 1s of the bonding time. The higher the bonding temperature the faster the ramp up of temperature is. A dynamic mechanical analysis (DMA) has been carried out to investigate the nature of the changes of the physical properties of the coupled anisotropic conductive-nonconductive adhesive film for a range of bonding parameters. Adhesive samples that are pre-cured at 170, 190 and 210°C for 3, 5 and 10s have been analyzed using a DMA instrument. The results have revealed that the glass transition temperature of this type of adhesive increases with the increase in the bonding time for the bonding temperatures that have been used in this work. For the curing time of 3 and 5s, the maximum glass transition temperature increases with the increase in the bonding temperature, but for the curing time of 10s the maximum glass transition temperature has been observed in the sample which is cured at 190°C. Based on these results it has been concluded that the optimal bonding temperature and time for this kind of adhesive are 190°C and 10s, respectively.

Rheological characterisation of solder pastes and isotropic conductive adhesives used for flip-chip assembly

Solder pastes and isotropic conductive adhesives (ICAs) are widely used as a principal bonding medium in the electronic industry. This study investigates the rheological behaviour of the pastes (solder paste and isotropic conductive adhesives) used for flip-chip assembly. Oscillatory stress sweep test are performed to evaluate solid characteristic and cohesiveness of the lead-free solder pastes and isotropic conductive adhesive paste materials. The results show that the G' (storage modulus) is higher than G '' (loss modulus) for the pastes material indicating a solid like behaviour. It result shows that the linear visco-elastic region for the pastes lies in a very small stress range, below 10 Pa. in addition, the stress at which the value of storage modulus is equal to that of loss modulus can be used as an indicator of the paste cohesiveness. The measured cross-over stress at G'=G '' shows that the solder paste has higher stress at G'=G '' compared to conductive adhesives. Creep-recovery test method is used to study the slump behaviour in the paste materials. The conductive adhesive paste shows a good recovery when compared to the solder pastes. (C) 2008 Elsevier B.V. All rights reserved.

Investigation of wall-slip effect on paste release characteristic in flip-chip stencil printing process

As the trend toward further miniaturisation of pocket and handheld consumer electronic products continues apace, the requirements for even smaller solder joints will continue. With further reductions in the size of solder joints, the reliability of solder joints will become more and more critical to the long-term performance of electronic products. Solder joints play an important role in electronics packaging, serving both as electrical interconnections between the components and the board, and as mechanical support for components. With world-wide legislation for the removal/reduction of lead and other hazardous materials from electrical and electronic products, the electronics manufacturing industry has been faced with an urgent search for new lead-free solder alloy systems and other solder alternatives. In order to achieve high volume, low cost production, the stencil printing process and subsequent wafer bumping of solder paste has become indispensable. There is wide agreement in industry that the paste printing process accounts for the majority of assembly defects, and most defects originate from poor understanding of the effect of printing process parameters on printing performance. The printing of ICAs and lead-free solder pastes through the very small stencil apertures required for flip chip applications was expected to result in increased stencil clogging and incomplete transfer of paste to the printed circuit pads. Paste release from the stencil apertures is dependent on the interaction between the solder paste, surface pad and aperture wall; including its shape. At these very narrow aperture sizes the paste rheology becomes crucial for consistent paste withdrawal because for smaller paste volumes surface tension effects become dominant over viscous flow. Successful aperture filling and release will greatly depend on the rheology of the paste material. Wall-slip plays an important role in characterising the flow behaviour of solder paste materials. The wall- slip arises due to the various attractive and repulsive forces acting between the solder particles and the walls of the measuring geometry. These interactions could lead to the presence of a thin solvent layer adjacent to the wall, which gives rise to slippage. The wall slip effect can play an important role in ensuring successful paste release after the printing process. The aim of this study was to investigate the influence of the paste microstructure on slip formation for the paste materials (lead-free solder paste and isotropic conductive adhesives). The effect of surface roughness on the paste viscosity was investigated. It was also found that altering the surface roughness of the parallel plate measuring geometry did not significantly eliminate wall slip as was expected. But results indicate that the use of a relatively rough surface helps to increase paste adhesion to the plates, inducing structural breakdown of the paste. Most importantly, the study also demonstrated on how the wall slip formation in the paste material could be utilised for understanding of the paste microstructure and its flow behaviour

Thermal Strain Analysis of a Flip-Chip Package by a Modified Hybrid Method

介绍一种可用于微电子封装局部应变场分析的实验/计算混合方法,该方法结合了有限元的整体/局部模型和实时的激光云纹干涉技术,利用激光云纹干涉技术所测得的应变场来校核有限元整体模型的计算结果,并用整体模型的结果作为局部模型的边界条件,对实验难以确定的封装结构局部位置的应力、应变场进行分析.用这种方法对可控坍塌倒装封装结构在热载荷作用下焊球内的应变场分布进行了分析,结果表明该方法能够提供封装结构内应力-应变场分布的准确和可靠的结果,为微电子封装的可靠性分析提供重要的依据. For the reliability analysis of electronic packages, strains in very localized areas, such as an interconnection or a corner, need to be determined. In this paper, a modified hybrid method of global/local modeling and real time moire interferometry is presented. In this method, a simplified, coarsely meshed global model is developed to get rough information about the deformation of the microelectronic package. In order to make sure the global model has been reasonably simplified and the material properties ...

Flip-chip bonded hybrid CMOS/SEED optoelectronic smart pixels

Hybrid integration of GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays are demonstrated flip-chip bonded directly onto 1 mu m silicon CMOS circuits. The GaAs/AlGaAs MQW devices are designed for 850 nm operation. Some devices are used as input light detectors and others serve as output light modulators. The measurement results under applied biases show good optoelectronic characteristics of elements in SEED arrays. Nearly the same reflection spectrum is obtained for the different devices at an array and the contrast ratio is more than 1.2:1 after flip-chip bonding and packaging. The transimpedance receiver-transmitter circuit can be operated at a frequency of 300 MHz.

Multiple Quantum Well SEED Arrays for Flip-Chip Bonding Optoelectronic Smart Pixels

于2010-11-23批量导入

Optoelectronic Smart Pixels Comprising Flip-Chip-Bonded GaAs/AlGaAs MQW Detectors and Modulators on Silicon CMOS Circuit

于2010-11-23批量导入