基于CAN的工业机器人内部通信总线设计

介绍了一种基于CAN总线的分布式工业机器人控制器的研究开发情况,实现了总线与各模块的接口设计,并制定出相应的机器人控制器内部通信协议。这种机器人控制器布线简单,系统可灵活扩展,有效提高了工业机器人的性能。

基于现场总线的工业机器人联网

本文根据国内工业机器人技术开发和应用现状及其技术发展趋势 ,进行了基于现场总线的工业机器人联网技术的研究和开发 ,并将机器人作为生产线底层设备 ,实现了工业机器人网络的互联 .本文介绍了这个系统的硬件结构、上位监控机软件实现、控制器软件实现以及系统完成的功能 .

WAGO750模块与PC机之间的通讯

介绍了一种用于WAGO750-842以太网节点及系列模块与PC机之间的一种通用而又简便的通讯方法,该方法能够使PC机与WAGO750系列模块方便地进行数据交换,从而达到计算机对控制对象进行信息采集和控制输出的目的。该方法已在载人潜水器控制系统中得到成功应用,效果良好。

模糊控制在现场总线控制系统中的应用

介绍了如何把模糊控制算法与现场总线中的CAN总线结合起来应用于控制系统 ,并设计了一种智能型模糊控制算法 ,给出了系统的整体结构和现场模糊控制单元的硬件实现电路及其软件设计思路 ;系统的仿真结果表明 ,该系统实时性好 ,控制精度较高 ,鲁棒性强 ,在现场控制中有效可行

SJA1000在数据采集与控制系统中的应用

本文介绍了一种新型的现场总线控制器ＳＪＡ １０００的基本结构及其功能特点，简要叙述了ＳＪＡ１０００与ＡＴ８９Ｃ５１组成的在基于ＣＡＮ总线的分布式数据采集与控制系统中的硬件接口电路和工作原理，最后还给出了通信程序清单。

Unveiling fieldbus network technology through project-based learning

Fieldbus communications networks are a fundamental part of modern industrial automation technique. This paperwork presents an application of project-based learning (PBL) paradigm to help electrical engineering students grasp the major concepts of fieldbus networks, while attending a one-term long, elective microcontroller course. © 2012 IEEE.

Performance analysis of PTP components for IEC 61850 process bus applications

New substation automation applications, such as sampled value process buses and synchrophasors, require sampling accuracy of 1 µs or better. The Precision Time Protocol (PTP), IEEE Std 1588, achieves this level of performance and integrates well into Ethernet based substation networks. This paper takes a systematic approach to the performance evaluation of commercially available PTP devices (grandmaster, slave, transparent and boundary clocks) from a variety of manufacturers. The ``error budget'' is set by the performance requirements of each application. The ``expenditure'' of this error budget by each component is valuable information for a system designer. The component information is used to design a synchronization system that meets the overall functional requirements. The quantitative performance data presented shows that this testing is effective and informative. Results from testing PTP performance in the presence of sampled value process bus traffic demonstrate the benefit of a ``bottom up'' component testing approach combined with ``top down'' system verification tests. A test method that uses a precision Ethernet capture card, rather than dedicated PTP test sets, to determine the Correction Field Error of transparent clocks is presented. This test is particularly relevant for highly loaded Ethernet networks with stringent timing requirements. The methods presented can be used for development purposes by manufacturers, or by system integrators for acceptance testing. A sampled value process bus was used as the test application for the systematic approach described in this paper. The test approach was applied, components were selected, and the system performance verified to meet the application's requirements. Systematic testing, as presented in this paper, is applicable to a range of industries that use, rather than develop, PTP for time transfer.

A microscopic simulation model to estimate bus rapid transit station bus capacity

The Bus Rapid Transit (BRT) station is the interface between passengers and services. The station is crucial to line operation as it is typically the only location where buses can pass each other. Congestion may occur here when buses maneuvering into and out of the platform lane interfere with bus flow, or when a queue of buses forms upstream of the platform lane blocking the passing lane. Further, some systems include operation where express buses do not observe the station, resulting in a proportion of non-stopping buses. It is important to understand the operation of the station under this type of operation and its effect on BRT line capacity. This study uses microscopic traffic simulation modeling to treat the BRT station operation and to analyze the relationship between station bus capacity and BRT line bus capacity. First, the simulation model is developed for the limit state scenario and then a statistical model is defined and calibrated for a specified range of controlled scenarios of dwell time characteristics. A field survey was conducted to verify the parameters such as dwell time, clearance time and coefficient of variation of dwell time to obtain relevant station bus capacity. The proposed model for BRT bus capacity provides a better understanding of BRT line capacity and is useful to transit authorities in BRT planning, design and operation.

An analysis of the impact of bus contention on the WCET in multicores

The use of multicores is becoming widespread inthe field of embedded systems, many of which have real-time requirements. Hence, ensuring that real-time applications meet their timing constraints is a pre-requisite before deploying them on these systems. This necessitates the consideration of the impact of the contention due to shared lowlevel hardware resources like the front-side bus (FSB) on the Worst-CaseExecution Time (WCET) of the tasks. Towards this aim, this paper proposes a method to determine an upper bound on the number of bus requests that tasks executing on a core can generate in a given time interval. We show that our method yields tighter upper bounds in comparison with the state of-the-art. We then apply our method to compute the extra contention delay incurred by tasks, when they are co-scheduled on different cores and access the shared main memory, using a shared bus, access to which is granted using a round-robin arbitration (RR) protocol.

WCET analysis considering contention on memory bus in COTS-based multicores

The usage of COTS-based multicores is becoming widespread in the field of embedded systems. Providing realtime guarantees at design-time is a pre-requisite to deploy real-time systems on these multicores. This necessitates the consideration of the impact of the contention due to shared low-level hardware resources on the Worst-Case Execution Time (WCET) of the tasks. As a step towards this aim, this paper first identifies the different factors that make the WCET analysis a challenging problem in a typical COTS-based multicore system. Then, we propose and prove, a mathematically correct method to determine tight upper bounds on the WCET of the tasks, when they are co-scheduled on different cores.

Vidibus: a low-cost, modular bus system for real-time video processing

The advantages of standard bus systems have been appreciated for many years. The ability to connect only those modules required to perform a given task has both technical and commercial advantages over a system with a fixed architecture which cannot be easily expanded or updated. Although such bus standards have proliferated in the microprocessor field, a general purpose low-cost standard for digital video processing has yet to gain acceptance. The paper describes the likely requirements of such a system, and discusses three currently available commercial systems. A new bus specification known as Vidibus, developed to fulfil these requirements, is presented. Results from applications already implemented using this real-time bus system are also given.

Contributions of ergonomics to the construction of bus drivers health and excellence in public transport and at work

This article is the product of research that analyzed the work of bus drivers of a public transportation company that is considered a benchmark reference in its field of operations, in which it strives to achieve operating excellence. Within this context, the authors sought to understand how such a company has managed to maintain a policy that is capable of reconciling quality public transport while also providing working conditions compatible with the professional development, comfort and health of its workers. Ergonomic work analysis and activity analysis were the guiding elements used in this study. Initial analyses indicate that the activity of drivers includes serving a population and providing mobility for it, which depends on driving the vehicle itself and on relationships with colleagues, users, pedestrians, drivers and others.

Translating bus information into sign language for deaf people

This paper describes the application of language translation technologies for generating bus information in Spanish Sign Language (LSE: Lengua de Signos Española). In this work, two main systems have been developed: the first for translating text messages from information panels and the second for translating spoken Spanish into natural conversations at the information point of the bus company. Both systems are made up of a natural language translator (for converting a word sentence into a sequence of LSE signs), and a 3D avatar animation module (for playing back the signs). For the natural language translator, two technological approaches have been analyzed and integrated: an example-based strategy and a statistical translator. When translating spoken utterances, it is also necessary to incorporate a speech recognizer for decoding the spoken utterance into a word sequence, prior to the language translation module. This paper includes a detailed description of the field evaluation carried out in this domain. This evaluation has been carried out at the customer information office in Madrid involving both real bus company employees and deaf people. The evaluation includes objective measurements from the system and information from questionnaires. In the field evaluation, the whole translation presents an SER (Sign Error Rate) of less than 10% and a BLEU greater than 90%.

A Dynamically Adaptable Bus Architecture for Trading-Off Among Performance, Consumption and Dependability in Cyber-Physical Systems

Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. Therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo3, which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy, multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented. A configuration-aware data transaction unit permits data dispatching to more than one module in parallel, or provide coalesced data dispatching among different units to maximize the advantages of burst transactions. The selection of a given configuration is application independent but context-aware, which may be achieved by the combination of a multi-thread model similar to the CUDA kernel model specification, combined with a dynamic thread/task/kernel scheduler. A multi-kernel application for face recognition is used as an application example to show one scenario of the ARTICo3 architecture.

Quantum gate based on Stark tunable nanocrystal interactions with ultrahigh-Q/V field modes in fused silica microcavities

We investigate the use of nanocrystal quantum dots as a quantum bus element for preparing various quantum resources for use in photonic quantum technologies. Using the Stark-tuning property of nanocrystal quantum dots as well as the biexciton transition, we demonstrate a photonic controlled-NOT (CNOT) interaction between two logical photonic qubits comprising two cavity field modes each. We find the CNOT interaction to be a robust generator of photonic Bell states, even with relatively large biexciton losses. These results are discussed in light of the current state of the art of both microcavity fabrication and recent advances in nanocrystal quantum dot technology. Overall, we find that such a scheme should be feasible in the near future with appropriate refinements to both nanocrystal fabrication technology and microcavity design. Such a gate could serve as an active element in photonic-based quantum technologies.