High performance VLSI architecture for Wave Digital Filtering

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders. © 1992 Kluwer Academic Publishers.

Pipelined two-port adaptor for wave digital filtering

The application of fine-grain pipelining techniques in the design of high-performance wave digital filters (WDFs) is described. The problems of latency in feedback loops can be significantly reduced if computations are organized most significant, as opposed to least significant, bit first and if the results are fed back as soon as they are formed. The result is that chips can be designed which offer significantly higher sampling rates than otherwise can be obtained using conventional methods. How these concepts can be extended to the more challenging problem of WDFs is discussed. It is shown that significant increases in the sampling rate of bit-parallel circuits can be achieved using most significant bit first arithmetic.

Systolic two-port adaptor for high performance wave digital filtering

The authors present a VLSI circuit for implementing wave digital filter (WDF) two-port adaptors. Considerable speedups over conventional designs have been obtained using fine grained pipelining. This has been achieved through the use of most significant bit (MSB) first carry-save arithmetic, which allows systems to be designed in which latency L is small and independent of either coefficient or input data wordlength. L is determined by the online delay associated with the computation required at each node in the circuit (in this case a multiply/add plus two separate additions). This in turn means that pipelining can be used to considerably enhance the sampling rate of a recursive digital filter. The level of pipelining which will offer enhancement is determined by L and is fine-grained rather than bit level. In the case of the circuit considered, L = 3. For this reason pipeline delays (half latches) have been introduced between every two rows of cells to produce a system with a once every cycle sample rate.

Digital filtering of oscillations intrinsic to transmission line modeling based on lumped parameters

A correction procedure based on digital signal processing theory is proposed to smooth the numeric oscillations in electromagnetic transient simulation results from transmission line modeling based on an equivalent representation by lumped parameters. The proposed improvement to this well-known line representation is carried out with an Finite Impulse Response (FIR) digital filter used to exclude the high-frequency components associated with the spurious numeric oscillations. To prove the efficacy of this correction method, a well-established frequency-dependent line representation using state equations is modeled with an FIR filter included in the model. The results obtained from the state-space model with and without the FIR filtering are compared with the results simulated by a line model based on distributed parameters and inverse transforms. Finally, the line model integrated with the FIR filtering is also tested and validated based on simulations that include nonlinear and time-variable elements. © 2012 Elsevier Ltd. All rights reserved.

Digital filtering using burst processing techniques /

Thesis (M. S.)--University of Illinois at Urbana-Champaign.

Wave digital filter model of the entire auditory periphery

A model of the auditory periphery assembled from analog network submodels of all the relevant anatomical structures is described. There is bidirectional coupling between networks representing the outer ear, middle ear and cochlea. A simple voltage source representation of the outer hair cells provides level-dependent basilar membrane curves. The networks are translated into efficient computational modules by means of wave digital filtering. A feedback unit regulates the average firing rate at the output of an inner hair cell module via a simplified modelling of the dynamics of the descending paths to the peripheral ear. This leads to a digital model of the entire auditory periphery with applications to both speech and hearing research.

Algorithms and architectures for high performance recursive filtering

Recently, a number of most significant digit (msd) first bit parallel multipliers for recursive filtering have been reported. However, the design approach which has been used has, in general, been heuristic and consequently, optimality has not always been assured. In this paper, msd first multiply accumulate algorithms are described and important relationships governing the dependencies between latency, number representations, etc are derived. A more systematic approach to designing recursive filters is illustrated by applying the algorithms and associated relationships to the design of cascadable modules for high sample rate IIR filtering and wave digital filtering.

Filtragem digital e reconstrução de sinais em frequência intermediária usando FPGA

O presente trabalho trata da filtragem e reconstrução de sinais em frequência intermediária usando FPGA. É feito o desenvolvimento de algoritmos usando processamento digital de sinais e também a implementação dos mesmos, constando desde o projeto da placa de circuito impresso, montagem e teste. O texto apresenta um breve estudo de amostragem e reconstrução de sinais em geral. Especial atenção é dada à amostragem de sinais banda-passante e à análise de questões práticas de reconstrução de sinais em frequência intermediária. Dois sistemas de reconstrução de sinais baseados em processamento digital de sinais, mais especificamente reamostragem no domínio discreto, são apresentados e analisados. São também descritas teorias de processos de montagem e soldagem de placas eletrônicas com objetivo de definir uma metodologia de projeto, montagem e soldagem de placas eletrônicas. Tal metodologia é aplicada no projeto e manufatura do protótipo de um módulo de filtragem digital para repetidores de telefonia celular. O projeto, implementado usando FPGA, é baseado nos dois sistemas supracitados. Ao final do texto, resultados obtidos em experimentos de filtragem digital e reconstrução de sinais em frequência intermediária com o protótipo desenvolvido são apresentados.