From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1

The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.

DESIGN AND TEST OF A 7-T SPLIT-PAIR MAGNET FOR MAGNETIC SEPARATION

A 160 mm bore, 7 T split-pair magnet was constructed and tested aiming to mineral processing through HGMS (high gradient magnetic separation) or HCMS (helical channel magnetic separation.) This work describes the design and test results of the pair of coils operating under current in parallel mode. In the case of antiparallel current mode large repulsive force between coils is generated and a strong magnetic field gradient outside the magnet is created. A continuous magnetic separation system made with a helical channel magnetic separator for application in TiO2 processing is analysed.

Design and Test of a 0.5 THz Dipole Antenna With Integrated Schottky Diode Detector on a High Dielectric Constant Ceramic Electromagnetic Bandgap Substrate

This paper presents the first analysis of the input impedance and radiation properties of a dipole antenna, placed on top of Fan 's three-dimensional electromagnetic bandgap (EBG) structure, (Applied Physics Letters, 1994) constructed using a high dielectric constant ceramic. The best position of the dipole on the EBG surface is determined following impedance and radiation pattern analyses. Based on this optimum configuration an integrated Schottky heterodyne detector was designed, manufactured and tested from 0.48 to 0.52 THz. The main antenna features were not degraded by the high dielectric constant substrate due to the use of the EBG approach. Measured radiation patterns are in good agreement with the predicted ones.

Design and Test of a High QoS Radio Network for CBTC Systems in Subway Tunnels

Communications Based Train Control Systems require high quality radio data communications for train signaling and control. Actually most of these systems use 2.4GHz band with proprietary radio transceivers and leaky feeder as distribution system. All them demand a high QoS radio network to improve the efficiency of railway networks. We present narrow band, broad band and data correlated measurements taken in Madrid underground with a transmission system at 2.4 GHz in a test network of 2 km length in subway tunnels. The architecture proposed has a strong overlap in between cells to improve reliability and QoS. The radio planning of the network is carefully described and modeled with narrow band and broadband measurements and statistics. The result is a network with 99.7% of packets transmitted correctly and average propagation delay of 20ms. These results fulfill the specifications QoS of CBTC systems.

Using front-end and formative evaluation to design and test persuasive bird feeding warning signs

Wildlife feeding is a wide-spread and controversial practice that can pose serious threats to the safety of both wildlife and visitors. The design and effectiveness of warning signs in recreational areas varies considerably and is rarely the product of theoretical models or scientific research. This study uses front-end and formative evaluation to design and test the perceived effectiveness of warning signs relating to bird feeding. Stage One examined visitors' beliefs, attitudes and bird feeding behaviour and found significant differences between feeders and non-feeders. Stage Two involved designing and evaluating three signs that built on the beliefs, knowledge and mis/conceptions identified in Stage One. Respondents thought the sign that focused on the birds' health and safety would be the most persuasive, however, elements of the other two signs were also positively evaluated. The article concludes with recommendations for the wording of future bird feeding warning signs. (c) 2004 Elsevier Ltd. All rights reserved.

Creating New Design-Build-Test Experiences as Outputs of Undergraduate Design-Build-Test Projects

This paper describes a methodology of using individual engineering undergraduate student projects as a means of effectively and efficiently developing new Design-Build-Test (DBT) learning experiences and challenges.
A key aspect of the rationale for this approach is that it benefits all parties. The student undertaking the individual project gets an authentic experience of producing a functional artefact, which has been the result of a design process that addresses conception, design, implementation and operation. The supervising faculty member benefits from live prototyping of new curriculum content and resources with a student who is at a similar level of knowledge and experience as the intended end users of the DBT outputs. The multiple students who ultimately undertake the DBT experiences / challenges benefit from the enhanced nature of a learning experience which has been “road tested” and optimised.
To demonstrate the methodology the paper will describe a case study example of an individual project completed in 2015. This resulted in a DBT design challenge with a theme of designing a catapult for throwing table tennis balls, the device being made from components laser cut from medium density fibreboard (MDF). Further three different modes of operation will be described which use the same resource materials but operate over different timescales and with different learning outcomes, from an icebreaker exercise focused on developing team dynamics through to full DBT where students get an opportunity to experience the full impact of their design decisions by competing against other students with a catapult they have designed and built themselves.

Enhancing the Manufacturing Knowledge of Undergraduate Engineering Students: A Case Study of a Design-Build-Test Challenge Involving Folding Bicycles

Many engineers currently in professional practice will have gained a degree level qualification which involved studying a curriculum heavy with mathematics and engineering science. While this knowledge is vital to the engineering design process so also is manufacturing knowledge, if the resulting designs are to be both technically and commercially viable.
The methodology advanced by the CDIO Initiative aims to improve engineering education by teaching in the context of Conceiving, Designing, Implementing and Operating products, processes or systems. A key element of this approach is the use of Design-Built-Test (DBT) projects as the core of an integrated curriculum. This approach facilitates the development of professional skills as well as the application of technical knowledge and skills developed in other parts of the degree programme. This approach also changes the role of lecturer to that of facilitator / coach in an active learning environment in which students gain concrete experiences that support their development.
The case study herein describes Mechanical Engineering undergraduate student involvement in the manufacture and assembly of concept and functional prototypes of a folding bicycle.

Design of a Test Stand for a Centrifugal Compressor

The goal of the Master’s thesis is to design a test stand for a centrifugal compressor. Different theoretical aspects of flow parameters measurements and test rigs built for the similar purposes in other research units are described in the theoretical part of the work. The process of components selection and the description of chosen components are given in the second part of the thesis. Besides measuring and control stages, the designed test stand has a closed-loop piping, an aftercooler and a surge tank. Overview and layout of the test rig is presented in the last chapter of the work.

Inverse aerodynamic design applications using the MGM hybrid formulation

The well-known modified Garabedian-Mcfadden (MGM) method is an attractive alternative for aerodynamic inverse design, for its simplicity and effectiveness (P. Garabedian and G. Mcfadden, Design of supercritical swept wings, AIAA J. 20(3) (1982), 289-291; J.B. Malone, J. Vadyak, and L.N. Sankar, Inverse aerodynamic design method for aircraft components, J. Aircraft 24(2) (1987), 8-9; Santos, A hybrid optimization method for aerodynamic design of lifting surfaces, PhD Thesis, Georgia Institute of Technology, 1993). Owing to these characteristics, the method has been the subject of several authors over the years (G.S. Dulikravich and D.P. Baker, Aerodynamic shape inverse design using a Fourier series method, in AIAA paper 99-0185, AIAA Aerospace Sciences Meeting, Reno, NV, January 1999; D.H. Silva and L.N. Sankar, An inverse method for the design of transonic wings, in 1992 Aerospace Design Conference, No. 92-1025 in proceedings, AIAA, Irvine, CA, February 1992, 1-11; W. Bartelheimer, An Improved Integral Equation Method for the Design of Transonic Airfoils and Wings, AIAA Inc., 1995). More recently, a hybrid formulation and a multi-point algorithm were developed on the basis of the original MGM. This article discusses applications of those latest developments for airfoil and wing design. The test cases focus on wing-body aerodynamic interference and shock wave removal applications. The DLR-F6 geometry is picked as the baseline for the analysis.

Design, Science and Conceptual Analysis

Philosophers expend considerable effort on the analysis of concepts, but the value of such work is not widely appreciated. This paper principally analyses some arguments, beliefs, and presuppositions about the nature of design and the relations between design and science common in the literature to illustrate this point, and to contribute to the foundations of design theory.

Methods of Design and Testing of Real Time Systems

Teollusuussovelluksissa vaaditaan nykyisin yhä useammin reaaliaikaista tiedon käsittelyä. Luotettavuus on yksi tärkeimmistä reaaliaikaiseen tiedonkäsittelyyn kykenevän järjestelmän ominaisuuksista. Sen saavuttamiseksi on sekä laitteisto, että ohjelmisto testattava. Tämän työn päätavoitteena on laitteiston testaaminen ja laitteiston testattavuus, koska luotettava laitteistoalusta on perusta tulevaisuuden reaaliaikajärjestelmille. Diplomityössä esitetään digitaaliseen signaalinkäsittelyyn soveltuvan prosessorikortin suunnittelu. Prosessorikortti on tarkoitettu sähkökoneiden ennakoivaa kunnonvalvontaa varten. Uusimmat DFT (Desing for Testability) menetelmät esitellään ja niitä sovelletaan prosessorikortin sunnittelussa yhdessä vanhempien menetelmien kanssa. Kokemukset ja huomiot menetelmien soveltuvuudesta raportoidaan työn lopussa. Työn tavoitteena on kehittää osakomponentti web -pohjaiseen valvontajärjestelmään, jota on kehitetty Sähkötekniikan osastolla Lappeenrannan teknillisellä korkeakoululla.

Reuse-based test planning for core-based systems-on-chip

Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.

Design of microprogrammed controllers with address converter implemented on programmable systems with embedded memories

In the paper the improvement of a traditional structure of a microprogrammed controller with sharing codes is discussed. The idea is based on the modification of internal modules and connections of the device. Such a solution permits to reduce the number of embedded memories needed for implementation of the microprogrammed controller on programmable structures, especially FPGAs. © 2011 IEEE.