Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

Decimal Multiplication using compact BCD Multiplier

Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.

Fixed Point Decimal Multiplication Using RPS Algorithm

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. A novel design for single digit decimal multiplication that reduces the critical path delay and area for an iterative multiplier is proposed in this research. The partial products are generated using single digit multipliers, and are accumulated based on a novel RPS algorithm. This design uses n single digit multipliers for an n × n multiplication. The latency for the multiplication of two n-digit Binary Coded Decimal (BCD) operands is (n + 1) cycles and a new multiplication can begin every n cycle. The accumulation of final partial products and the first iteration of partial product generation for next set of inputs are done simultaneously. This iterative decimal multiplier offers low latency and high throughput, and can be extended for decimal floating-point multiplication.

Influence of the Operational Constraints in the Active Transmission Losses Allocation via Lagrange Multipliers

This paper presents an approach for the active transmission losses allocation between the agents of the system. The approach uses the primal and dual variable information of the Optimal Power Flow in the losses allocation strategy. The allocation coefficients are determined via Lagrange multipliers. The paper emphasizes the necessity to consider the operational constraints and parameters of the systems in the problem solution. An example, for a 3-bus system is presented in details, as well as a comparative test with the main allocation methods. Case studies on the IEEE 14-bus systems are carried out to verify the influence of the constraints and parameters of the system in the losses allocation.

A cross-cultural study on the effect of decimal separator on price perception

A Work Project, presented as part of the requirements for the Award of a Masters Degree in Management from the NOVA – School of Business and Economics

Fiscal multipliers in Portugal using a threshold approach

A Work Project, presented as part of the requirements for the Award of a Masters Degree in Economics from the NOVA – School of Business and Economics

The role of income inequality on fiscal multipliers

A Work Project, presented as part of the requirements for the Award of a Masters Double Degree in Economics from the Nova School of Business and Economics and University of Maastricht

The Distribution Dynamics of Output Multipliers in Scotland 1998–2007

In an input-output context the impact of any particular industrial sector is commonly measured in terms of the output multiplier for that industry. Although such measures are routinely calculated and often used to guide regional industrial policy the behaviour of such measures over time is an area that has attracted little academic study. The output multipliers derived from any one table will have a distribution; for some industries the multiplier will be relatively high, for some it will be relatively low. The recentpublication of consistent input-output tables for the Scottish economy makes it possible to examine trends in this mdistribution over the ten year period 1998-2007. This is done by comparing the means and other summary measures of the distributions, the histograms and the cumulative densities. The results indicate a tendency for the multipliers to increase over the period. A Markov chain modelling approach suggests that this drift is a slow but long term phenomenon which appears not to tend to an equilibrium state. The prime reason for the increase in the output multipliers is traced to a decline in the relative importance of imported (both from the rest of the UK and the rest of the world) intermediate inputs used by Scottish industries. This suggests that models calibrated on the set of tables might have to be interpreted with caution.

Type II Errors in IO Multipliers

This paper compares methods for calculating Input-Output (IO) Type II multipliers. These are formulations of the standard Leontief IO model which endogenise elements of household consumption. An analytical comparison of the two basic IO Type II multiplier methods with the Social Accounting Matrix (SAM) multiplier approach identifies the treatment of non-wage income generated in production as a central problem. The multiplier values for each of the IO and SAM methods are calculated using Scottish data for 2009. These results can be used to choose which Type II IO multiplier to adopt where SAM multiplier values are unavailable.

Fiscal multipliers in a two-sector search and matching model

This paper evaluates the effects of policy interventions on sectoral labour markets and the aggregate economy in a business cycle model with search and matching frictions. We extend the canonical model by including capital-skill complementarity in production, labour markets with skilled and unskilled workers and on-the-job-learning (OJL) within and across skill types. We first find that, the model does a good job at matching the cyclical properties of sectoral employment and the wage-skill premium. We next find that vacancy subsidies for skilled and unskilled jobs lead to output multipliers which are greater than unity with OJL and less than unity without OJL. In contrast, the positive output effects from cutting skilled and unskilled income taxes are close to zero. Finally, we find that the sectoral and aggregate effects of vacancy subsidies do not depend on whether they are financed via public debt or distorting taxes.

The Analysis of Accounting Multipliers: The NAMEA Approach in the Case of Catalonia

The aim of this paper is the analysis of the Catalan economy (2001) with the use of a National Accounting Matrix with environmental accounts (NAMEA) for the Catalan economy with 2001 data. We will focus on the analysis of the emission multipliers and we will also analyse the impact of a 10% reduction in greenhouse emissions on emission multipliers. This emission-reduction percentage would bring the Catalan economy into compliance with the maximum emissions level allowed by the Kyoto Protocol. We consider three possible scenarios that would allow this goal to be met. First, we will simulate a 10% reduction in regional emissions and a 5% drop in the endogenous income of the multipliers' model (production, factorial and private income). Second, we will simulate a 10% reduction in emissions and a 10% increase in endogenous income. Finally, we will simulate a 10% reduction in emissions and a 5% increase in endogenous income. Additionally, we will analyse the decomposition of the emission multipliers into own effects, open effects and circular effects to capture the different channels of the emission generation process. Keywords: NAMEA, emission multipliers, Kyoto Protocol.

Budget constrained expenditure multipliers

We show that standard expenditure multipliers capture economy-wide effects of new government projects only when financing constraints are not binding. In actual policy making, however, new projects usually need financing. Under liquidity constraints, new projects are subject to two opposite effects: an income effect and a set of spending substitution effects. The former is the traditional, unrestricted, multiplier effect; the latter is the result of expenditure reallocation to upheld effective financing constraints. Unrestricted multipliers will therefore be, as a general rule, upward biased and policy designs based upon them should be reassessed in the light of the countervailing substitution effects.

Some conceptual difficulties regarding "net" multipliers

Multipliers are routinely used for impact evaluation of private projects and public policies at the national and subnational levels. Oosterhaven and Stelder (2002) correctly pointed out the misuse of standard 'gross' multipliers and proposed the concept of 'net' multiplier as a solution to this bad practice. We prove their proposal is not well founded. We do so by showing that supporting theorems are faulty in enunciation and demonstration. The proofs are flawed due to an analytical error but the theorems themselves cannot be salvaged as generic, non-curiosum counterexamples demonstrate. We also provide a general analytical framework for multipliers and, using it, we show that standard 'gross' multipliers are all that is needed within the interindustry model since they follow the causal logic of the economic model, are well defined and independent of exogenous shocks, and are interpretable as predictors for change.