An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology

Chronic recording of neural signals is indispensable in designing efficient brain–machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode–neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal–oxide–semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 $mu{rm A}$, modulating input referred noise from 9.92 $mu{rm V}$ to 3.9 $mu{rm V}$. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.

Development of CMOS-compatible electrostatic supercapacitors

This work focuses on development of electrostatic supercapacitors (ESCs) using process routes compatible with complementary metal–oxide–semiconductor (CMOS) fabrication. Wafer-scale anodised aluminium oxide (AAO) processing techniques have been developed to produce high-surface area templates. Statistically optimised atomic layer deposition (ALD) processes have been developed to conformally coat the templates and generate metalinsulator-metal capacitor structures. Detailed electrical characterisation and analysis for a range of devices, revealed ESC’s with high capacitance densities of ~12 μF cm-2 and equivalent energy densities of 0.28 Wh/kg . Finally the suitability of ESC’s toward next generation energy storage applications is discussed.

Advanced numerical characterization of silicon with defect by nanoindentation

Nano silicon is widely used as the essential element of complementary metal–oxide–semiconductor (CMOS) and solar cells. It is recognized that today, large portion of world economy is built on electronics products and related services. Due to the accessible fossil fuel running out quickly, there are increasing numbers of researches on the nano silicon solar cells. The further improvement of higher performance nano silicon components requires characterizing the material properties of nano silicon. Specially, when the manufacturing process scales down to the nano level, the advanced components become more and more sensitive to the various defects induced by the manufacturing process. It is known that defects in mono-crystalline silicon have significant influence on its properties under nanoindentation. However, the cost involved in the practical nanoindentation as well as the complexity of preparing the specimen with controlled defects slow down the further research on mechanical characterization of defected silicon by experiment. Therefore, in current study, the molecular dynamics (MD) simulations are employed to investigate the mono-crystalline silicon properties with different pre-existing defects, especially cavities, under nanoindentation. Parametric studies including specimen size and loading rate, are firstly conducted to optimize computational efficiency. The optimized testing parameters are utilized for all simulation in defects study. Based on the validated model, different pre-existing defects are introduced to the silicon substrate, and then a group of nanoindentation simulations of these defected substrates are carried out. The simulation results are carefully investigated and compared with the perfect Silicon substrate which used as benchmark. It is found that pre-existing cavities in the silicon substrate obviously influence the mechanical properties. Furthermore, pre-existing cavities can absorb part of the strain energy during loading, and then release during unloading, which possibly causes less plastic deformation to the substrate. However, when the pre-existing cavities is close enough to the deformation zone or big enough to exceed the bearable stress of the crystal structure around the spherical cavity, the larger plastic deformation occurs which leads the collapse of the structure. Meanwhile, the influence exerted on the mechanical properties of silicon substrate depends on the location and size of the cavity. Substrate with larger cavity size or closer cavity position to the top surface, usually exhibits larger reduction on Young’s modulus and hardness.

Investigation of the hazards of substrate current injection: transient external latchup and substrate noise coupling

Substrate current injection is the origin of external latchup and substrate noise coupling. The trigger current for external latchup depends on the duration of the trigger event. A physics-based model is provided to model the effects of aggressor to victim spacing and orientation on transient triggering of external latchup. The latchup susceptibility of standard cell based designs is also investigated. Guard rings are used to reduce latchup susceptibility and to reduce the substrate noise coupled to sensitive analog circuits. In this work, the effectiveness of different guard ring topologies for the reduction of substrate noise coupling is also investigated.

One step self-aligned multilayer patterning process for the fabrication of organic complementary circuits in combination with inkjet printing

Recent development of solution processable organic semiconductors delineates the emergence of a new generation of air-stable, high performance p- and n-type materials. This makes it indeed possible for printed organic complementary circuits (CMOS) to be used in real applications. The main technical bottleneck for organic CMOS to be adopted as the next generation organic integrated circuit is how to deposit and pattern both p- and n-type semiconductor materials with high resolutions at the same time. It represents a significant technical challenge, especially if it can be done for multiple layers without mask alignment. In this paper, we propose a one-step self-aligned fabrication process which allows the deposition and high resolution patterning of functional layers for both p- and n-channel thin film transistors (TFTs) simultaneously. All the dimensional information of the device components is featured on a single imprinting stamp, and the TFT-channel geometry, electrodes with different work functions, p- and n-type semiconductors and effective gate dimensions can all be accurately defined by one-step imprinting and the subsequent pattern transfer process. As an example, we have demonstrated an organic complementary inverter fabricated by 3D imprinting in combination with inkjet printing and the measured electrical characteristics have validated the feasibility of the novel technique. © 2012 Elsevier B.V. All rights reserved.

Integration of room temperature single electron transistor with CMOS subsystem

The single electron transistor (SET) is a charge-based device that may complement the dominant metal-oxide-semiconductor field effect transistor (MOSFET) technology. As the cost of scaling MOSFET to smaller dimensions are rising and the the basic functionality of MOSFET is encountering numerous challenges at dimensions smaller than 10nm, the SET has shown the potential to become the next generation device which operates based on the tunneling of electrons. Since the electron transfer mechanism of a SET device is based on the non-dissipative electron tunneling effect, the power consumption of a SET device is extremely low, estimated to be on the order of 10^-18J. The objectives of this research are to demonstrate technologies that would enable the mass produce of SET devices that are operational at room temperature and to integrate these devices on top of an active complementary-MOSFET (CMOS) substrate. To achieve these goals, two fabrication techniques are considered in this work. The Focus Ion Beam (FIB) technique is used to fabricate the islands and the tunnel junctions of the SET device. A Ultra-Violet (UV) light based Nano-Imprint Lithography (NIL) call Step-and-Flash- Imprint Lithography (SFIL) is used to fabricate the interconnections of the SET devices. Combining these two techniques, a full array of SET devices are fabricated on a planar substrate. Test and characterization of the SET devices has shown consistent Coulomb blockade effect, an important single electron characteristic. To realize a room temperature operational SET device that function as a logic device to work along CMOS, it is important to know the device behavior at different temperatures. Based on the theory developed for a single island SET device, a thermal analysis is carried out on the multi-island SET device and the observation of changes in Coulomb blockade effect is presented. The results show that the multi-island SET device operation highly depends on temperature. The important parameters that determine the SET operation is the effective capacitance Ceff and tunneling resistance Rt . These two parameters lead to the tunneling rate of an electron in the SET device, Γ. To obtain an accurate model for SET operation, the effects of the deviation in dimensions, the trap states in the insulation, and the background charge effect have to be taken into consideration. The theoretical and experimental evidence for these non-ideal effects are presented in this work.

Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

Smart chemical sensor application of ZnO nanowires grown on CMOS compatible SOI microheater platform

Smart chemical sensor based on CMOS(complementary metal-oxide- semiconductor) compatible SOI(silicon on insulator) microheater platform was realized by facilitating ZnO nanowires growth on the small membrane at the relatively low temperature. Our SOI microheater platform can be operated at the very low power consumption with novel metal oxide sensing materials, like ZnO or SnO2 nanostructured materials which demand relatively high sensing temperature. In addition, our sol-gel growth method of ZnO nanowires on the SOI membrane was found to be very effective compared with ink-jetting or CVD growth techniques. These combined techniques give us the possibility of smart chemical sensor technology easily merged into the conventional semiconductor IC application. The physical properties of ZnO nanowire network grown by the solution-based method and its chemical sensing property also were reported in this paper.

Laminar to turbulent flow transition measurements using an array of SOI-CMOS MEMS wall shear stress sensors

The successful utilization of an array of silicon on insulator complementary metal oxide semiconductor (SOICMOS) micro thermal shear stress sensors for flow measurements at macro-scale is demonstrated. The sensors use CMOS aluminum metallization as the sensing material and are embedded in low thermal conductivity silicon oxide membranes. They have been fabricated using a commercial 1 μm SOI-CMOS process and a post-CMOS DRIE back etch. The sensors with two different sizes were evaluated. The small sensors (18.5 ×18.5 μm2 sensing area on 266 × 266 μm2 oxide membrane) have an ultra low power (100 °C temperature rise at 6mW) and a small time constant of only 5.46 μs which corresponds to a cut-off frequency of 122 kHz. The large sensors (130 × 130 μm2 sensing area on 500 × 500 μm2 membrane) have a time constant of 9.82 μs (cut-off frequency of 67.9 kHz). The sensors' performance has proven to be robust under transonic and supersonic flow conditions. Also, they have successfully identified laminar, separated, transitional and turbulent boundary layers in a low speed flow. © 2008 IEEE.

Improved infrared thermal imaging of a CMOS MEMS device

We report a technique which can be used to improve the accuracy of infrared (IR) surface temperature measurements made on MEMS (Micro-Electro-Mechanical- Systems) devices. The technique was used to thermally characterize a SOI (Silicon-On-Insulator) CMOS (Complementary Metal Oxide Semiconductor) MEMS thermal flow sensor. Conventional IR temperature measurements made on the sensor were shown to give significant surface temperature errors, due to the optical transparency of the SiO 2 membrane layers and low emissivity/high reflectivity of the metal. By making IR measurements on radiative carbon micro-particles placed in isothermal contact with the device, the accuracy of the surface temperature measurement was significantly improved. © 2010 EDA Publishing/THERMINIC.

Thermal characterization of SOI CMOS micro hot-plate gas sensors

This work reports on thermal characterization of SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) MEMS (micro electro mechanical system) gas sensors using a thermoreflectance (TR) thermography system. The sensors were fabricated in a CMOS foundry and the micro hot-plate structures were created by back-etching the CMOS processed wafers in a MEMS foundry using DRIE (deep reactive ion etch) process. The calibration and experimental details of the thermoreflectance based thermal imaging setup, used for these micro hot-plate gas sensor structures, are presented. Experimentally determined temperature of a micro hot-plate sensor, using TR thermography and built-in silicon resistive temperature sensor, is compared with that estimated using numerical simulations. The results confirm that TR based thermal imaging technique can be used to determine surface temperature of CMOS MEMS devices with a high accuracy. © 2010 EDA Publishing/THERMINIC.

Complementary metal-oxide-semiconductor-compatible and self-aligned catalyst formation for carbon nanotube synthesis and interconnect fabrication

We have for the first time developed a self-aligned metal catalyst formation process using fully CMOS (complementary metal-oxide-semiconductor) compatible materials and techniques, for the synthesis of aligned carbon nanotubes (CNTs). By employing an electrically conductive cobalt disilicide (CoSi 2) layer as the starting material, a reactive ion etch (RIE) treatment and a hydrogen reduction step are used to transform the CoSi 2 surface into cobalt (Co) nanoparticles that are active to catalyze aligned CNT growth. Ohmic contacts between the conductive substrate and the CNTs are obtained. The process developed in this study can be applied to form metal nanoparticles in regions that cannot be patterned using conventional catalyst deposition methods, for example at the bottom of deep holes or on vertical surfaces. This catalyst formation method is crucially important for the fabrication of vertical and horizontal interconnect devices based on CNTs. © 2012 American Institute of Physics.

SOI CMOS integrated zinc oxide nanowire for toluene detection

The paper reports on the in-situ growth of zinc oxide nanowires (ZnONWs) on a complementary metal oxide semiconductor (CMOS) substrate, and their performance as a sensing element for ppm (parts per million) levels of toluene vapour in 3000 ppm humid air. Zinc oxide NWs were grown using a low temperature (only 90°C) hydrothermal method. The ZnONWs were first characterised both electrically and through scanning electron microscopy. Then the response of the on-chip ZnONWs to different concentrations of toluene (400-2600ppm) was observed in air at 300°C. Finally, their gas sensitivity was determined and found to lie between 0.1% and 0.3% per ppm. © 2013 IEEE.

A thermopile based SOI CMOS MEMS wall shear stress sensor

In this paper we present for the first time, a novel silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) MEMS thermal wall shear stress sensor based on a tungsten hot-film and three thermopiles. These devices have been fabricated using a commercial 1 μm SOI-CMOS process followed by a deep reactive ion etch (DRIE) back-etch step to create silicon oxide membranes under the hot-film for effective thermal isolation. The sensors show an excellent repeatability of electro-thermal characteristics and can be used to measure wall shear stress in both constant current anemometric as well as calorimetric modes. The sensors have been calibrated for wall shear stress measurement of air in the range of 0-0.48 Pa using a suction type, 2-D flow wind tunnel. The calibration results show that the sensors have a higher sensitivity (up to four times) in calorimetric mode compared to anemometric mode for wall shear stress lower than 0.3 Pa. © 2013 IEEE.