Slot coupled sqaure microstrip antenna for compact dual-frequency operation

A novel dual frequency design of a square microstrip antenna coaxially fed along the diagonal with a chip capacitor mounted at the bottom of the stub is introduced. This design provides enhanced area reduction and good cross-polarization levels. The antenna design can be used as a compact antenna system where limited size is a major requirement. The details of the antenna design and experimental results are presented

Design, fabrication, and evaluation of on-chip micro-supercapacitors

Due to the increasing demand for high power and reliable miniaturized energy storage devices, the development of micro-supercapacitors or electrochemical micro-capacitors have attracted much attention in recent years. This dissertation investigates several strategies to develop on-chip micro-supercapacitors with high power and energy density. Micro-supercapacitors based on interdigitated carbon micro-electrode arrays are fabricated through carbon microelectromechanical systems (C-MEMS) technique which is based on carbonization of patterned photoresist. To improve the capacitive behavior, electrochemical activation is performed on carbon micro-electrode arrays. The developed micro-supercapacitors show specific capacitances as high as 75 mFcm-2 at a scan rate of 5 mVs -1 after electrochemical activation for 30 minutes. The capacitance loss is less than 13% after 1000 cyclic voltammetry (CV) cycles. These results indicate that electrochemically activated C-MEMS micro-electrode arrays are promising candidates for on-chip electrochemical micro-capacitor applications. The energy density of micro-supercapacitors was further improved by conformal coating of polypyrrole (PPy) on C-MEMS structures. In these types of micro-devices the three dimensional (3D) carbon microstructures serve as current collectors for high energy density PPy electrodes. The electrochemical characterizations of these micro-supercapacitors show that they can deliver a specific capacitance of about 162.07 mFcm-2 and a specific power of 1.62mWcm -2 at a 20 mVs-1 scan rate. Addressing the need for high power micro-supercapacitors, the application of graphene as electrode materials for micro-supercapacitor was also investigated. The present study suggests a novel method to fabricate graphene-based micro-supercapacitors with thin film or in-plane interdigital electrodes. The fabricated micro-supercapacitors show exceptional frequency response and power handling performance and could effectively charge and discharge at rates as high as 50 Vs-1. CV measurements show that the specific capacitance of the micro-supercapacitor based on reduced graphene oxide and carbon nanotube composites is 6.1 mFcm -2 at scan rate of 0.01Vs-1. At a very high scan rate of 50 Vs-1, a specific capacitance of 2.8 mFcm-2 (stack capacitance of 3.1 Fcm-3) is recorded. This unprecedented performance can potentially broaden the future applications of micro-supercapacitors.

A novel high voltage pulsed power supply based on low voltage switch-capacitor units

This paper presents a high voltage pulsed power system based on low voltage switch-capacitor units connected to a current source for several applications such as plasma systems. A buck-boost converter topology is used to utilize the current source and a series of low voltage switch-capacitor units is connected to the current source in order to provide high voltage with high voltage stress (dv/dt) as demanded by loads. This pulsed power converter is flexible in terms of energy control, in that the stored energy in the current source can be adjusted by changing the current magnitude to significantly improve the efficiency of various systems with different requirements. Output voltage magnitude and stress (dv/dt) can be controlled by a proper selection of components and control algorithm to turn on and off switching devices.

Flying-capacitor-based chopper circuit for DC capacitor voltage balancing in diode-clamped multilevel inverter

This paper proposes a flying-capacitor-based chopper circuit for dc capacitor voltage equalization in diode-clamped multilevel inverters. Its important features are reduced voltage stress across the chopper switches, possible reduction in the chopper switching frequency, improved reliability, and ride-through capability enhancement. This topology is analyzed using three- and four-level flying-capacitor-based chopper circuit configurations. These configurations are different in capacitor and semiconductor device count and correspondingly reduce the device voltage stresses by half and one-third, respectively. The detailed working principles and control schemes for these circuits are presented. It is shown that, by preferentially selecting the available chopper switch states, the dc-link capacitor voltages can be efficiently equalized in addition to having tightly regulated flying-capacitor voltages around their references. The various operating modes of the chopper are described along with their preferential selection logic to achieve the desired performances. The performance of the proposed chopper and corresponding control schemes are confirmed through both simulation and experimental investigations.

Torsional Interaction Studies on a Power System Compensated by SSSC and Fixed Capacitor

In this paper, a static synchronous series compensator (SSSC), along with a fixed capacitor, is used to avoid torsional mode instability in a series compensated transmission system. A 48-step harmonic neutralized inverter is used for the realization of the SSSC. The system under consideration is the IEEE first benchmark model on SSR analysis. The system stability is studied both through eigenvalue analysis and EMTDC/PSCAD simulation studies. It is shown that the combination of the SSSC and the fixed capacitor improves the synchronizing power coefficient. The presence of the fixed capacitor ensures increased damping of small signal oscillations. At higher levels of fixed capacitor compensation, a damping controller is required to stabilize the torsional modes of SSR.

Control schemes for equalization of capacitor voltages in neutral clamped shunt compensator

Voltage imbalance in capacitors is a well-known problem in compensator topologies which use two or more capacitors. This imbalance may exist even if the load does not contain any DC component, due to practical factors. However, when the load contains a DC part, the voltage imbalance problem becomes critical. In this paper, a two-quadrant chopper has been used to regulate the capacitor voltages in a two-capacitor compensator structure. Two different control strategies for the two-quadrant chopper to equalize the voltage of the capacitors have been proposed. The strategies are validated through detailed simulation studies. Experiments have also been carried out to validate the hysteresis control of chopper.

Static shunt and series compensations of an SMIB system using flying capacitor multilevel inverter

The flying capacitor multilevel inverter (FCMLI) is a multiple voltage level inverter topology intended for high-power and high-voltage operations at low distortion. It uses capacitors, called flying capacitors, to clamp the voltage across the power semiconductor devices. A method for controlling the FCMLI is proposed which ensures that the flying capacitor voltages remain nearly constant using the preferential charging and discharging of these capacitors. A static synchronous compensator (STATCOM) and a static synchronous series compensator (SSSC) based on five-level flying capacitor inverters are proposed. Control schemes for both the FACTS controllers are developed and verified in terms of voltage control, power flow control, and power oscillation damping when installed in a single-machine infinite bus (SMIB) system. Simulation studies are performed using PSCAD/EMTDC to validate the efficacy of the control scheme and the FCMLI-based flexible alternating current transmission system (FACTS) controllers.

Design of a capacitor supported dynamic voltage restorer (DVR) for unbalanced and distorted loads

The paper discusses the operating principles and control characteristics of a dynamic voltage restorer (DVR) that protects sensitive but unbalanced and/or distorted loads. The main aim of the DVR is to regulate the voltage at the load terminal irrespective of sag/swell, distortion, or unbalance in the supply voltage. In this paper, the DVR is operated in such a fashion that it does not supply or absorb any active power during the steady-state operation. Hence, a DC capacitor rather than a DC source can supply the voltage source inverter realizing the DVR. The proposed DVR operation is verified through extensive digital computer simulation studies.

A novel high voltage pulsed power supply based on low voltage switch-capacitor units

This paper presents a high voltage pulsed power system based on low voltage switch-capacitor units connected to a current source for several applications such as plasma systems. A modified positive buck-boost converter topology is used to utilize the current source concept and a series of low voltage switch-capacitor units is connected to the current source in order to provide high voltage with high voltage stress (dv/dt) as demanded by loads. This pulsed power converter is flexible in terms of energy control, in that the stored energy in the current source can be adjusted by changing the current magnitude to significantly improve the efficiency of various systems with different requirements. Output voltage magnitude and stress (dv/dt) can be controlled by a proper selection of components and control algorithm to turn on and off switching devices.

Theoretical analysis of serrated chip formation based on ideal models in high speed cutting

In this paper, two ideal formation models of serrated chips, the symmetric formation model and the unilateral right-angle formation model, have been established for the first time. Based on the ideal models and related adiabatic shear theory of serrated chip formation, the theoretical relationship among average tooth pitch, average tooth height and chip thickness are obtained. Further, the theoretical relation of the passivation coefficient of chip's sawtooth and the chip thickness compression ratio is deduced as well. The comparison between these theoretical prediction curves and experimental data shows good agreement, which well validates the robustness of the ideal chip formation models and the correctness of the theoretical deducing analysis. The proposed ideal models may have provided a simple but effective theoretical basis for succeeding research on serrated chip morphology. Finally, the influences of most principal cutting factors on serrated chip formation are discussed on the basis of a series of finite element simulation results for practical advices of controlling serrated chips in engineering application.