Generative Serienproduktion von Mikrokomponenten

Stetig steigende Funktionalitäten, intelligente Materialien, eine möglichst geringe Leistungsaufnahme verbunden mit kleinem Volumen und geringem Gewicht sind die zentralen Anforderungen u.a. der Medizintechnik und der Telekommunikation. Um diesen Bedarf mit industriellen Fertigungsverfahren abzudecken, startete das Unternehmen nach seiner Gründung in Rumeln bereits 1996 mit dem Aufbau der RMPD® Technologiefamilie. Heute sichern diese Technologien, mit denen die direkte Serienproduktion auf Basis der CAD Kontruktionsdaten für Mikrosysteme und –komponenten werkzeuglos erfolgt, einem internationalen Kundenkreis Markterfolge mit dem Einsatz patentierter Fertigungssysteme. microTEC ist an zwei Standorten als Auftragsproduzent für Unternehmen u.a. aus den Bereichen Sensorik, Telekommunikation, Medizintechnik und Biotechnologie tätig. Mit den RMPD® Technologien profitieren die Kunden auch durch die schnelle Anpassungsfähigkeit an sich ändernde Marktbedingungen und Verbraucherwünsche. Über 300 Kunststoffe mit den unterschiedlichsten Eigenschaften stehen für mikroelektronische Packaging-Dienstleistungen und Auftragsfertigung von Mikrosystemen zur Verfügung, zu den Produkten gehören z.B. Mikrogetriebe mit selbstschmierenden Zahnrädern und Lab-on-a-Chipsysteme, die mit dem Einsatz hydrophiler Kunststoffe die Kapillarwirkung auch in 3D nutzen. Die beiden Geschäftsführer Dipl. Ing. Reiner Götzen und Andrea Reinhardt, sowie der Prokurist Dr. Ing. Helge Bohlmann stehen für eine konzernunabhängige, kundenorientierte Strategie und verfügen über langjährige Erfahrung als mittelständische Unternehmer. Dies bildet zusammen mit der internationalen Marktorientierung, dem branchenübergreifenden Technologie Know-how und den inhouse verfügbaren Produktionsanlagen die Basis für den weiteren Standortausbau im 8. Jahr des Unternehmens.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

Response variation of optically stimulated luminescence dosimeters

Introduction This study investigates uncertainties pertaining to the use of optically stimulated luminescence dosimeters (OSLDs) in radiotherapy dosimetry. The sensitivity of the luminescent material is related to the density of recombination centres [1], which is in the range of 1015–1016 cm-3. Because of this non-uniform distribution of traps in crystal growth the sensitivity varies substantially within a batch of dosimeters. However, a quantitative understanding of the relationship between the response of an OSLD and its sensitive volume has not yet been investigated or reported in literature. Methods In this work, OSLDs are scanned with a MicroCT scanner to determine potential sources for the variation in relative sensitivity across a selection of Landauer nanoDot dosimeters. Specifically, the correlation between a dosimeters relative sensitivity and the loading density of Al2O3:C powder was determined. Results When extrapolating the sensitive volume’s radiodensity from the CT data, it was shown that there is a non-uniform distribution incrystal growth as illustrated in Fig. 1. A plot of voxel count versus the element-specific correction factor is shown in Fig. 2 where each point represents a single OSLD. A line was fitted which has an R2-value of 0.69 and a P-value of 8.21 9 10-19. This data shows that the response of a dosimeter decreases proportionally with sensitive volume. Extrapolating from this data, a quantitative relationship between response and sensitive volume was roughly determined for this batch of dosimeters. A change in volume of 1.176 9 10-5 cm3 corresponds to a 1 % change in response. In other words, a 0.05 % change in the nominal volume of the chip would result in a 1 % change in response. Discussion and conclusions This work demonstrated that the amount of sensitive material is approximately linked to the total correction factor. Furthermore, the ‘true’ volume of an OSLD’s sensitive material is, on average, 17.90 % less than that which has been reported in literature, mainly due to the presence of air cavities in the material’s structure. Finally, the potential effects of the inaccuracy of Al2O3:C deposition increases with decreasing chip size. If a luminescent dosimeter were manufactured with a smaller volume than currently employed using the same manufacturing protocol, the variation in response from chip to chip would more than likely exceed the current 5 % range.

Design and fabrication of compact nonblocking 4X4 optical matrix switch on silicon-on-insulator by anisotropic chemical etching

A folding nonblocking 4 X 4 optical matrix switch in simplified-tree architecture was designed and fabricated on a silicon-on-insulator wafer. To compress chip size, switch elements (SEs) were connected by total internal reflection mirrors instead of conventional S-bends. For obtaining smooth interfaces, potassium hydroxide (KOH) anisotropic chemical etching of silicon was employed. The device has a compact size of 20 X 3.2 mm(2) and a fast response of 8 +/- 1 mu s. Power consumption of 2 x 2 SE and excess loss per mirror were 145 mW and -1.1 dB, respectively. (c) 2005 Society of Photo-Optical Instrumentation Engineers.

Integrated folding 4x4 optical matrix switch with total internal reflection mirrors on SOI by anisotropic chemical etching

A folding rearrangeable nonblocking 4 x 4 optical matrix switch was designed and fabricated on silicon-on-insulator wafer. To compress chip size, switch elements (SEs) were interconnected by total internal reflection (TIR) mirrors instead of conventional S-bends. For obtaining smooth interfaces, potassium hydroxide anisotropic chemical etching of silicon was utilized to make the matrix switch for the first time. The device has a compact size of 20 x 1.6 mm(2) and a fast response of 7.5 mu s. The power consumption of each 2 x 2 SE and the average excess loss per mirror were 145 mW and -1.1 dB, respectively. Low path dependence of +/- 0.7 dB in total excess loss was obtained because of the symmetry of propagation paths in this novel matrix switch.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

Dimensões de cavacos industriais de eucalipto e relações com polpação, resistência e morfologia de fibras na polpa

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Toward a Scalable Working Set Size Estimation Method and Its Application for Chip Multiprocessors

It is essential to accurately estimate the working set size (WSS) of an application for various optimizations such as to partition cache among virtual machines or reduce leakage power dissipated in an over-allocated cache by switching it OFF. However, the state-of-the-art heuristics such as average memory access latency (AMAL) or cache miss ratio (CMR) are poorly correlated to the WSS of an application due to 1) over-sized caches and 2) their dispersed nature. Past studies focus on estimating WSS of an application executing on a uniprocessor platform. Estimating the same for a chip multiprocessor (CMP) with a large dispersed cache is challenging due to the presence of concurrently executing threads/processes. Hence, we propose a scalable, highly accurate method to estimate WSS of an application. We call this method ``tagged WSS (TWSS)'' estimation method. We demonstrate the use of TWSS to switch-OFF the over-allocated cache ways in Static and Dynamic NonUniform Cache Architectures (SNUCA, DNUCA) on a tiled CMP. In our implementation of adaptable way SNUCA and DNUCA caches, decision of altering associativity is taken by each L2 controller. Hence, this approach scales better with the number of cores present on a CMP. It gives overall (geometric mean) 26% and 19% higher energy-delay product savings compared to AMAL and CMR heuristics on SNUCA, respectively.

High-resolution strain sensing on steel by Silicon-On-Insulator flexural resonators fabricated with chip-level vacuum packaging

This paper reports on the fabrication and characterization of high-resolution strain sensors for steel based on Silicon On Insulator flexural resonators manufactured with chip-level LPCVD vacuum packaging. The sensors present high sensitivity (120 Hz/μ), very high resolution (4 n), low drift, and near-perfect reversibility in bending tests performed in both tensile and compressive strain regimes. © 2013 IEEE.

Effect of solder volume on joint shape with variable chip-to-board contact pad ratio

The objective of this paper is to investigate the effect of the pad size ratio between the chip and board end of a solder joint on the shape of that solder joint in combination with the solder volume available. The shape of the solder joint is correlated to its reliability and thus of importance. For low density chip bond pad applications Flip Chip (FC) manufacturing costs can be kept down by using larger size board pads suitable for solder application. By using “Surface Evolver” software package the solder joint shapes associated with different size/shape solder preforms and chip/board pad ratios are predicted. In this case a so called Flip-Chip Over Hole (FCOH) assembly format has been used. Assembly trials involved the deposition of lead-free 99.3Sn0.7Cu solder on the board side, followed by reflow, an underfill process and back die encapsulation. During the assembly work pad off-sets occurred that have been taken into account for the Surface Evolver solder joint shape prediction and accurately matched the real assembly. Overall, good correlation was found between the simulated solder joint shape and the actual fabricated solder joint shapes. Solder preforms were found to exhibit better control over the solder volume. Reflow simulation of commercially available solder preform volumes suggests that for a fixed stand-off height and chip-board pad ratio, the solder volume value and the surface tension determines the shape of the joint.

Integrated spot size converters for InP based photonic systems

The ever increasing demand for broadband communications requires sophisticated devices. Photonic integrated circuits (PICs) are an approach that fulfills those requirements. PICs enable the integration of different optical modules on a single chip. Low loss fiber coupling and simplified packaging are key issues in keeping the price of PICs at a low level. Integrated spot size converters (SSC) offer an opportunity to accomplish this. Design, fabrication and characterization of SSCs based on an asymmetric twin waveguide (ATG) at a wavelength of 1.55 μm are the main elements of this dissertation. It is theoretically and experimentally shown that a passive ATG facilitates a polarization filter mechanism. A reproducible InP process guideline is developed that achieves vertical waveguides with smooth sidewalls. Birefringence and resonant coupling are used in an ATG to enable a polarization filtering and splitting mechanism. For the first time such a filter is experimentally shown. At a wavelength of 1610 nm a power extinction ratio of (1.6 ± 0.2) dB was measured for the TE- polarization in a single approximately 372 μm long TM- pass polarizer. A TE-pass polarizer with a similar length was demonstrated with a TM/TE-power extinction ratio of (0.7 ± 0.2) dB at 1610 nm. The refractive indices of two different InGaAsP compositions, required for a SSC, are measured by the reflection spectroscopy technique. A SSC layout for dielectric-free fabricated compact photodetectors is adjusted to those index values. The development and the results of the final fabrication procedure for the ATG concept are outlined. The etch rate, sidewall roughness and selectivity of a Cl2/CH4/H2 based inductively coupled plasma (ICP) etch are investigated by a design of experiment approach. The passivation effect of CH4 is illustrated for the first time. Conditions are determined for etching smooth and vertical sidewalls up to a depth of 5 μm.

Computational modelling for reliable flip-chip packaging at sub-100 micron pitch using isotropic conductive adhesives

This paper presents the assembly process using next generation electroformed stencils and Isotropic Conductive Adhesives (ICAs) as interconnection material. The utilisation of ICAs in flip-chip assembly process is investigated as an alternative to the lead and lead-free solder alloys and aims to ensure a low temperature (T < 100 °C) assembly process. The paper emphasizes and discusses in details the assembly of a flip-chip package based on copper columns bumped die and substrate with stencil printed ICA deposits at sub-100 μm pitch. A computational modelling approach is undertaken to provide comprehensive results on reliability trends of ICA joints subject to thermal cycling of the flip-chip assembly based on easy to use damage criteria and damage evaluation. Important design parameters in the package are selected and investigated using numerical modelling techniques to provide knowledge and understanding of their impact on the thermo-mechanical behaviour of the flip-chip ICA joints. Sensitivity analysis of the damage in the adhesive material is also carried out. Optimal design rules for enhanced performance and improved thermo-mechanical reliability of ICA assembled flip-chip packages are finally formulated.

Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process

This paper presents the results of a packaging process based on the stencil printing of isotropic conductive adhesives (ICAs) that form the interconnections of flip-chip bonded electronic packages. Ultra-fine pitch (sub-100-mum), low temperature (100degC), and low cost flip-chip assembly is demonstrated. The article details recent advances in electroformed stencil manufacturing that use microengineering techniques to enable stencil fabrication at apertures sizes down to 20mum and pitches as small as 30mum. The current state of the art for stencil printing of ICAs and solder paste is limited between 150-mum and 200-mum pitch. The ICAs-based interconnects considered in this article have been stencil printed successfully down to 50-mum pitch with consistent printing demonstrated at 90-mum pitch size. The structural integrity or the stencil after framing and printing is also investigated through experimentation and computational modeling. The assembly of a flip-chip package based on copper column bumped die and ICA deposits stencil printed at sub-100-mum pitch is described. Computational fluid dynamics modeling of the print performance provides an indicator on the optimum print parameters. Finally, an organic light emitting diode display chip is packaged using this assembly process

Investigation of wall-slip effect on paste release characteristic in flip-chip stencil printing process

As the trend toward further miniaturisation of pocket and handheld consumer electronic products continues apace, the requirements for even smaller solder joints will continue. With further reductions in the size of solder joints, the reliability of solder joints will become more and more critical to the long-term performance of electronic products. Solder joints play an important role in electronics packaging, serving both as electrical interconnections between the components and the board, and as mechanical support for components. With world-wide legislation for the removal/reduction of lead and other hazardous materials from electrical and electronic products, the electronics manufacturing industry has been faced with an urgent search for new lead-free solder alloy systems and other solder alternatives. In order to achieve high volume, low cost production, the stencil printing process and subsequent wafer bumping of solder paste has become indispensable. There is wide agreement in industry that the paste printing process accounts for the majority of assembly defects, and most defects originate from poor understanding of the effect of printing process parameters on printing performance. The printing of ICAs and lead-free solder pastes through the very small stencil apertures required for flip chip applications was expected to result in increased stencil clogging and incomplete transfer of paste to the printed circuit pads. Paste release from the stencil apertures is dependent on the interaction between the solder paste, surface pad and aperture wall; including its shape. At these very narrow aperture sizes the paste rheology becomes crucial for consistent paste withdrawal because for smaller paste volumes surface tension effects become dominant over viscous flow. Successful aperture filling and release will greatly depend on the rheology of the paste material. Wall-slip plays an important role in characterising the flow behaviour of solder paste materials. The wall- slip arises due to the various attractive and repulsive forces acting between the solder particles and the walls of the measuring geometry. These interactions could lead to the presence of a thin solvent layer adjacent to the wall, which gives rise to slippage. The wall slip effect can play an important role in ensuring successful paste release after the printing process. The aim of this study was to investigate the influence of the paste microstructure on slip formation for the paste materials (lead-free solder paste and isotropic conductive adhesives). The effect of surface roughness on the paste viscosity was investigated. It was also found that altering the surface roughness of the parallel plate measuring geometry did not significantly eliminate wall slip as was expected. But results indicate that the use of a relatively rough surface helps to increase paste adhesion to the plates, inducing structural breakdown of the paste. Most importantly, the study also demonstrated on how the wall slip formation in the paste material could be utilised for understanding of the paste microstructure and its flow behaviour