Nonvolatile multilevel data storage memory device from controlled ambipolar charge trapping mechanism

The capability of storing multi-bit information is one of the most important challenges in memory technologies. An ambipolar polymer which intrinsically has the ability to transport electrons and holes as a semiconducting layer provides an opportunity for the charge trapping layer to trap both electrons and holes efficiently. Here, we achieved large memory window and distinct multilevel data storage by utilizing the phenomena of ambipolar charge trapping mechanism. As fabricated flexible memory devices display five well-defined data levels with good endurance and retention properties showing potential application in printed electronics.

Influence of fluorine on radiation-induced charge trapping in the SIMOX buried oxides

Charge trapping in the fluorinated SIMOX buried oxides before and after ionizing radiation has been investigated by means of C-V characteristics. Radiation-induced positive charge trapping which results in negative shift of C-V curves can be restrained by implanting fluorine ions into the SIMOX buried oxides. Pre-radiation charge trapping is suppressed in the fluorinated buried oxides. The fluorine dose and post-implantation anneal time play a very important role in the control of charge trapping.

Performance improvement by charge trapping of doping fluorescent dyes in organic memory devices

We studied the memory effect in the devices consisting of dye-doped N, N'-di(naphthalene-1-yl)-N, N'-diphenyl-benzidine sandwiched between indium-tin oxide and Ag electrodes. It was found that the on/off current ratio was greatly improved by the doped fluorescent dyes compared with nondoping devices. A mechanism of charge trapping was demonstrated to explain the improvement of the memory effect. For the off state, the conduction process is dominated by the trapping current, which is a characteristic of the space-charge limited current, whereas the on state is dominated by the detrapping current, and interpreted by Poole-Frenkel emission.

Synchrotron-laser interactions in hexagonal boron nitride: an examination of charge trapping dynamics at the boron K-edge

Poolton, Nigel; Towlson, B.M.; Hamilton, B.; Evans, D.A., (2006) 'Synchrotron-laser interactions in hexagonal boron nitride: an examination of charge trapping dynamics at the boron K-edge', New Journal of Physics 8 pp.76 RAE2008

It’s a Trap! Unravelling Reversible Charge Trapping in Nanocrystals Through Single Particle and Ensemble Studies

Thesis (Ph.D.)--University of Washington, 2016-08

Technology and characterization of GaN-HEMTs devices: high temperature and trapping effects

Los transistores de alta movilidad electrónica basados en GaN han sido objeto de una extensa investigación ya que tanto el GaN como sus aleaciones presentan unas excelentes propiedades eléctricas (alta movilidad, elevada concentración de portadores y campo eléctrico crítico alto). Aunque recientemente se han incluido en algunas aplicaciones comerciales, su expansión en el mercado está condicionada a la mejora de varios asuntos relacionados con su rendimiento y habilidad. Durante esta tesis se han abordado algunos de estos aspectos relevantes; por ejemplo, la fabricación de enhancement mode HEMTs, su funcionamiento a alta temperatura, el auto calentamiento y el atrapamiento de carga. Los HEMTs normalmente apagado o enhancement mode han atraído la atención de la comunidad científica dedicada al desarrollo de circuitos amplificadores y conmutadores de potencia, ya que su utilización disminuiría significativamente el consumo de potencia; además de requerir solamente una tensión de alimentación negativa, y reducir la complejidad del circuito y su coste. Durante esta tesis se han evaluado varias técnicas utilizadas para la fabricación de estos dispositivos: el ataque húmedo para conseguir el gate-recess en heterostructuras de InAl(Ga)N/GaN; y tratamientos basados en flúor (plasma CF4 e implantación de F) de la zona debajo de la puerta. Se han llevado a cabo ataques húmedos en heteroestructuras de InAl(Ga)N crecidas sobre sustratos de Si, SiC y zafiro. El ataque completo de la barrera se consiguió únicamente en las muestras con sustrato de Si. Por lo tanto, se puede deducir que la velocidad de ataque depende de la densidad de dislocaciones presentes en la estructura, ya que el Si presenta un peor ajuste del parámetro de red con el GaN. En relación a los tratamientos basados en flúor, se ha comprobado que es necesario realizar un recocido térmico después de la fabricación de la puerta para recuperar la heteroestructura de los daños causados durante dichos tratamientos. Además, el estudio de la evolución de la tensión umbral con el tiempo de recocido ha demostrado que en los HEMTs tratados con plasma ésta tiende a valores más negativos al aumentar el tiempo de recocido. Por el contrario, la tensión umbral de los HEMTs implantados se desplaza hacia valores más positivos, lo cual se atribuye a la introducción de iones de flúor a niveles más profundos de la heterostructura. Los transistores fabricados con plasma presentaron mejor funcionamiento en DC a temperatura ambiente que los implantados. Su estudio a alta temperatura ha revelado una reducción del funcionamiento de todos los dispositivos con la temperatura. Los valores iniciales de corriente de drenador y de transconductancia medidos a temperatura ambiente se recuperaron después del ciclo térmico, por lo que se deduce que dichos efectos térmicos son reversibles. Se han estudiado varios aspectos relacionados con el funcionamiento de los HEMTs a diferentes temperaturas. En primer lugar, se han evaluado las prestaciones de dispositivos de AlGaN/GaN sobre sustrato de Si con diferentes caps: GaN, in situ SiN e in situ SiN/GaN, desde 25 K hasta 550 K. Los transistores con in situ SiN presentaron los valores más altos de corriente drenador, transconductancia, y los valores más bajos de resistencia-ON, así como las mejores características en corte. Además, se ha confirmado que dichos dispositivos presentan gran robustez frente al estrés térmico. En segundo lugar, se ha estudiado el funcionamiento de transistores de InAlN/GaN con diferentes diseños y geometrías. Dichos dispositivos presentaron una reducción casi lineal de los parámetros en DC en el rango de temperaturas de 25°C hasta 225°C. Esto se debe principalmente a la dependencia térmica de la movilidad electrónica, y también a la reducción de la drift velocity con la temperatura. Además, los transistores con mayores longitudes de puerta mostraron una mayor reducción de su funcionamiento, lo cual se atribuye a que la drift velocity disminuye más considerablemente con la temperatura cuando el campo eléctrico es pequeño. De manera similar, al aumentar la distancia entre la puerta y el drenador, el funcionamiento del HEMT presentó una mayor reducción con la temperatura. Por lo tanto, se puede deducir que la degradación del funcionamiento de los HEMTs causada por el aumento de la temperatura depende tanto de la longitud de la puerta como de la distancia entre la puerta y el drenador. Por otra parte, la alta densidad de potencia generada en la región activa de estos transistores conlleva el auto calentamiento de los mismos por efecto Joule, lo cual puede degradar su funcionamiento y Habilidad. Durante esta tesis se ha desarrollado un simple método para la determinación de la temperatura del canal basado en medidas eléctricas. La aplicación de dicha técnica junto con la realización de simulaciones electrotérmicas han posibilitado el estudio de varios aspectos relacionados con el autocalentamiento. Por ejemplo, se han evaluado sus efectos en dispositivos sobre Si, SiC, y zafiro. Los transistores sobre SiC han mostrado menores efectos gracias a la mayor conductividad térmica del SiC, lo cual confirma el papel clave que desempeña el sustrato en el autocalentamiento. Se ha observado que la geometría del dispositivo tiene cierta influencia en dichos efectos, destacando que la distribución del calor generado en la zona del canal depende de la distancia entre la puerta y el drenador. Además, se ha demostrado que la temperatura ambiente tiene un considerable impacto en el autocalentamiento, lo que se atribuye principalmente a la dependencia térmica de la conductividad térmica de las capas y sustrato que forman la heterostructura. Por último, se han realizado numerosas medidas en pulsado para estudiar el atrapamiento de carga en HEMTs sobre sustratos de SiC con barreras de AlGaN y de InAlN. Los resultados obtenidos en los transistores con barrera de AlGaN han presentado una disminución de la corriente de drenador y de la transconductancia sin mostrar un cambio en la tensión umbral. Por lo tanto, se puede deducir que la posible localización de las trampas es la región de acceso entre la puerta y el drenador. Por el contrario, la reducción de la corriente de drenador observada en los dispositivos con barrera de InAlN llevaba asociado un cambio significativo en la tensión umbral, lo que implica la existencia de trampas situadas en la zona debajo de la puerta. Además, el significativo aumento del valor de la resistencia-ON y la degradación de la transconductancia revelan la presencia de trampas en la zona de acceso entre la puerta y el drenador. La evaluación de los efectos del atrapamiento de carga en dispositivos con diferentes geometrías ha demostrado que dichos efectos son menos notables en aquellos transistores con mayor longitud de puerta o mayor distancia entre puerta y drenador. Esta dependencia con la geometría se puede explicar considerando que la longitud y densidad de trampas de la puerta virtual son independientes de las dimensiones del dispositivo. Finalmente se puede deducir que para conseguir el diseño óptimo durante la fase de diseño no sólo hay que tener en cuenta la aplicación final sino también la influencia que tiene la geometría en los diferentes aspectos estudiados (funcionamiento a alta temperatura, autocalentamiento, y atrapamiento de carga). ABSTRACT GaN-based high electron mobility transistors have been under extensive research due to the excellent electrical properties of GaN and its related alloys (high carrier concentration, high mobility, and high critical electric field). Although these devices have been recently included in commercial applications, some performance and reliability issues need to be addressed for their expansion in the market. Some of these relevant aspects have been studied during this thesis; for instance, the fabrication of enhancement mode HEMTs, the device performance at high temperature, the self-heating and the charge trapping. Enhancement mode HEMTs have become more attractive mainly because their use leads to a significant reduction of the power consumption during the stand-by state. Moreover, they enable the fabrication of simpler power amplifier circuits and high-power switches because they allow the elimination of negativepolarity voltage supply, reducing significantly the circuit complexity and system cost. In this thesis, different techniques for the fabrication of these devices have been assessed: wet-etching for achieving the gate-recess in InAl(Ga)N/GaN devices and two different fluorine-based treatments (CF4 plasma and F implantation). Regarding the wet-etching, experiments have been carried out in InAl(Ga)N/GaN grown on different substrates: Si, sapphire, and SiC. The total recess of the barrier was achieved after 3 min of etching in devices grown on Si substrate. This suggests that the etch rate can critically depend on the dislocations present in the structure, since the Si exhibits the highest mismatch to GaN. Concerning the fluorine-based treatments, a post-gate thermal annealing was required to recover the damages caused to the structure during the fluorine-treatments. The study of the threshold voltage as a function of this annealing time has revealed that in the case of the plasma-treated devices it become more negative with the time increase. On the contrary, the threshold voltage of implanted HEMTs showed a positive shift when the annealing time was increased, which is attributed to the deep F implantation profile. Plasma-treated HEMTs have exhibited better DC performance at room temperature than the implanted devices. Their study at high temperature has revealed that their performance decreases with temperature. The initial performance measured at room temperature was recovered after the thermal cycle regardless of the fluorine treatment; therefore, the thermal effects were reversible. Thermal issues related to the device performance at different temperature have been addressed. Firstly, AlGaN/GaN HEMTs grown on Si substrate with different cap layers: GaN, in situ SiN, or in situ SiN/GaN, have been assessed from 25 K to 550 K. In situ SiN cap layer has been demonstrated to improve the device performance since HEMTs with this cap layer have exhibited the highest drain current and transconductance values, the lowest on-resistance, as well as the best off-state characteristics. Moreover, the evaluation of thermal stress impact on the device performance has confirmed the robustness of devices with in situ cap. Secondly, the high temperature performance of InAlN/GaN HEMTs with different layouts and geometries have been assessed. The devices under study have exhibited an almost linear reduction of the main DC parameters operating in a temperature range from room temperature to 225°C. This was mainly due to the thermal dependence of the electron mobility, and secondly to the drift velocity decrease with temperature. Moreover, HEMTs with large gate length values have exhibited a great reduction of the device performance. This was attributed to the greater decrease of the drift velocity for low electric fields. Similarly, the increase of the gate-to-drain distance led to a greater reduction of drain current and transconductance values. Therefore, this thermal performance degradation has been found to be dependent on both the gate length and the gate-to-drain distance. It was observed that the very high power density in the active region of these transistors leads to Joule self-heating, resulting in an increase of the device temperature, which can degrade the device performance and reliability. A simple electrical method have been developed during this work to determine the channel temperature. Furthermore, the application of this technique together with the performance of electro-thermal simulations have enabled the evaluation of different aspects related to the self-heating. For instance, the influence of the substrate have been confirmed by the study of devices grown on Si, SiC, and Sapphire. HEMTs grown on SiC substrate have been confirmed to exhibit the lowest self-heating effects thanks to its highest thermal conductivity. In addition to this, the distribution of the generated heat in the channel has been demonstrated to be dependent on the gate-to-drain distance. Besides the substrate and the geometry of the device, the ambient temperature has also been found to be relevant for the self-heating effects, mainly due to the temperature-dependent thermal conductivity of the layers and the substrate. Trapping effects have been evaluated by means of pulsed measurements in AlGaN and InAIN barrier devices. AlGaN barrier HEMTs have exhibited a de crease in drain current and transconductance without measurable threshold voltage change, suggesting the location of the traps in the gate-to-drain access region. On the contrary, InAIN barrier devices have showed a drain current associated with a positive shift of threshold voltage, which indicated that the traps were possibly located under the gate region. Moreover, a significant increase of the ON-resistance as well as a transconductance reduction were observed, revealing the presence of traps on the gate-drain access region. On the other hand, the assessment of devices with different geometries have demonstrated that the trapping effects are more noticeable in devices with either short gate length or the gate-to-drain distance. This can be attributed to the fact that the length and the trap density of the virtual gate are independent on the device geometry. Finally, it can be deduced that besides the final application requirements, the influence of the device geometry on the performance at high temperature, on the self-heating, as well as on the trapping effects need to be taken into account during the device design stage to achieve the optimal layout.

Charge transfer and transport in DNA

We explore charge migration in DNA, advancing two distinct mechanisms of charge separation in a donor (d)–bridge ({Bj})–acceptor (a) system, where {Bj} = B1,B2, … , BN are the N-specific adjacent bases of B-DNA: (i) two-center unistep superexchange induced charge transfer, d*{Bj}a → d∓{Bj}a±, and (ii) multistep charge transport involves charge injection from d* (or d+) to {Bj}, charge hopping within {Bj}, and charge trapping by a. For off-resonance coupling, mechanism i prevails with the charge separation rate and yield exhibiting an exponential dependence ∝ exp(−βR) on the d-a distance (R). Resonance coupling results in mechanism ii with the charge separation lifetime τ ∝ Nη and yield Y ≃ (1 + δ̄ Nη)−1 exhibiting a weak (algebraic) N and distance dependence. The power parameter η is determined by charge hopping random walk. Energetic control of the charge migration mechanism is exerted by the energetics of the ion pair state d∓B1±B2 … BNa relative to the electronically excited donor doorway state d*B1B2 … BNa. The realization of charge separation via superexchange or hopping is determined by the base sequence within the bridge. Our energetic–dynamic relations, in conjunction with the energetic data for d*/d− and for B/B+, determine the realization of the two distinct mechanisms in different hole donor systems, establishing the conditions for “chemistry at a distance” after charge transport in DNA. The energetic control of the charge migration mechanisms attained by the sequence specificity of the bridge is universal for large molecular-scale systems, for proteins, and for DNA.

Trapping phenomena in AlGaN and InAlN barrier HEMTs with different geometries

PAPER Trapping phenomena in AlGaN and InAlN barrier HEMTs with different geometries S Martin-Horcajo1, A Wang1, A Bosca1, M F Romero1, M J Tadjer1,2, A D Koehler2, T J Anderson2 and F Calle1 Published 11 February 2015 • © 2015 IOP Publishing Ltd Semiconductor Science and Technology, Volume 30, Number 3 Article PDF Figures References Citations Metrics 350 Total downloads Cited by 1 articles Export citation and abstract BibTeX RIS Turn on MathJax Share this article Article information Abstract Trapping effects were evaluated by means of pulsed measurements under different quiescent biases for GaN/AlGaN/GaN and GaN/InAlN/GaN. It was found that devices with an AlGaN barrier underwent an increase in the on-resistance, and a drain current and transconductance reduction without measurable threshold voltage change, suggesting the location of the traps in the gate-drain access region. In contrast, devices with an InAlN barrier showed a transconductance and a decrease in drain associated with a significant positive shift of threshold voltage, indicating that the traps were likely located under the gate region; as well as an on-resistance degradation probably associated with the presence of surface traps in the gate-drain access region. Furthermore, measurements of drain current transients at different ambient temperatures revealed that the activation energy of electron traps was 0.43 eV and 0.38 eV for AlGaN and InAlN barrier devices, respectively. Experimental and simulation results demonstrated the influence of device geometry on the observed trapping effects, since devices with larger gate lengths and gate-to-drain distance values exhibited less noticeable charge trapping effects.

A study of the effects metal residues in poly(9,9-dioctylfluorene) have on field-effect transistor device characteristics

The amount of metal residues from organometallic reagents used in preparation of poly(9,9-dioctylfluorene) by palladium catalysed Suzuki and nickel-induced Yamamoto polycondensations have been determined, and their effect upon the behaviour of the polymer in field-effect transistors (FETs) has been measured. The metal levels from material polymerised by Suzuki method were found to be much higher than from that made by the Yamamoto procedure. Simple treatment of the polymers with suitable metal trapping reagents lowered the metal levels significantly, with EDTA giving best results for nickel and triphenylphosphine for palladium. Comparison of the behaviour of FETs using polyfluorenes with varying levels of metal contamination, showed that the metal residues have little effect upon the mobility values, but often affect the degree of hysteresis, possibly acting as charge traps. Satisfactory device performances were obtained from polymer with palladium levels of 2000 μg/g suggesting that complete removal of metal residues may not be necessary for satisfactory device performance.

Surface engineering of reduced graphene oxide for controllable ambipolar flash memories

Tunable charge-trapping behaviors including unipolar charge trapping of one type of charge carrier and ambipolar trapping of both electrons and holes in a complementary manner is highly desirable for low power consumption multibit flash memory design. Here, we adopt a strategy of tuning the Fermi level of reduced graphene oxide (rGO) through self-assembled monolayer (SAM) functionalization and form p-type and n-type doped rGO with a wide range of manipulation on work function. The functionalized rGO can act as charge-trapping layer in ambipolar flash memories, and a dramatic transition of charging behavior from unipolar trapping of electrons to ambipolar trapping and eventually to unipolar trapping of holes was achieved. Adjustable hole/electron injection barriers induce controllable Vth shift in the memory transistor after programming operation. Finally, we transfer the ambipolar memory on flexible substrates and study their charge-trapping properties at various bending cycles. The SAM-functionalized rGO can be a promising candidate for next-generation nonvolatile memories.

Role of lattice defects and crystallite morphology in the UV and visible-light-induced photo-catalytic properties of combustion-prepared TiO2

The physico-chemical, photo-physical and micro-structural properties responsible for the strikingly different photocatalytic behavior of combustion-prepared TiO2 (c.TiO2) and Degussa P25 (d.TiO2) samples are elucidated in this study. Electron microscopy and selected area electron diffraction micrographs revealed that the two samples exhibited different morphologies. The grains of c.TiO2 were spherical and comprised of 5-6 nm size primary particle. On the other hand, d.TiO2 consisted of large (0.5-3.0 mu m) size and irregular shape aggregates having primary particles of 15-40 nm cross-sectional diameter. The ESR study revealed that the presence of certain defect states in c.TiO2 helped in stabilization of O-. and Ti3+-OH type species during room-temperature UV-irradiation. No such paramagnetic species were however formed over d.TiO2 under similar conditions. C1s and Ti 2p XPS spectra provide evidence for the presence of some lattice vacancies in c.TiO2 and also for the bulk Ti4+ -> Ti3+ conversion during its UV-irradiation. Compared to d.TiO2, c.TiO2 displayed considerably higher activity for discoloration of methyl orange but very poor activity for splitting of water, both under UV and visible light radiations. This is attributed to enhanced surface adsorption of dye molecules over c.TiO2, because of its textural features and also the presence of photo-active ion-radicals. On the other hand, the poor activity of c.TiO2 for water splitting is related to certain defect-induced inter-band charge trapping states in the close vicinity of valence and conduction bands of c.TiO2, as revealed by thermoluminescence spectroscopy. Further, the dispersion of nanosize gold particles gave rise to augmented activity of both the catalysts, particularly for water splitting. This is explained by the promotional role of Au-0 or Au-0/TiO2 interfacial sites in the adsorption and charge-adsorbate interaction processes. (C) 2011 Elsevier B.V. All rights reserved.