Microstrip circular phased array design and development using microwave antenna CAD tools

The complex design and development of a planar multilayer phased array antenna in microstrip technology can be simplified using two commercially available design tools 1) Ansoft Ensemble and 2) HP-EEsof Touchstone. In the approach presented here, Touchstone is used to design RF switches and phase shifters whose scattering parameters are incorporated in Ensemble simulations using its black box tool. Using this approach, Ensemble is able to fully analyze the performance of radiating and beamforming layers of a phased array prior to its manufacturing. This strategy is demonstrated in a design example of a 12-element linearly-polarized circular phased array operating at L band. A comparison between theoretical and experimental results of the array is demonstrated.

Teaching Magnetic Design using CAD tools

Design of magnetic components is a multivariable problem. There are many different combinations of shapes, sizes and materials for the core with many diameters for the wires. So it is difficult to find the optimum design without a great number of iterations. Analytically only a few combinations are usually studied but it is very easy to take into account all the combinations using a CAD tool [1]. In this work the CAD tool used is PExprt (ANSYS [2]) which is being developed at UPMCEI.

SOFHIA: a CAD environment to design digital control systems

"Series Title: IFIP - The International Federation for Information Processing, ISSN 1868-4238"

Desarrollo de una guía de aprendizaje para el manejo del entorno de CAD IspLEVER

En este proyecto se analizan las características y el ciclo de diseño asociado al entorno de CAD IspLEVER, de Lattice Semiconductor, con la finalidad de evaluar su adecuación a la docencia relacionada con la ingeniería de sistemas digitales cableados. En base a este estudio se realiza una guía del manejo de las diferentes herramientas que se integran en el entorno. Además, se realiza la caracterización de una serie de familias de dispositivos del fabricante Lattice Semiconductor que pudiera servir de apoyo a la hora de elegir un dispositivo de este fabricante para la realización de un determinado diseño. Para dar comienzo a la realización del estudio del entorno y de las herramientas que integra IspLEVER, se procedió a la familiarización con el marco de trabajo. Esta familiarización se realizó, en un principio, a través de la lectura de la documentación ofrecida por el fabricante en su página web, http://www.latticesemi.com. Tras esta lectura, que sirvió para tener una primera visión de las características de la herramienta, se procedió a la descarga del paquete de instalación; el fabricante ofrece una versión de evaluación que expira a los 12 meses. Una vez descargado, se instaló y para terminar con los preparativos, se pasó el procedimiento de obtención de la licencia. Con ello se consiguió tener el software preparado para su utilización. A continuación se emplearon horas de trabajo para, sin documentación alguna, tratar de crear diseños; con este trabajo se pretendía detectar lo intuitivo que resulta el entorno cuando se tienen conocimientos de herramientas de CAD electrónico. Tras esta primera toma de contacto con el entorno real, se procedió al estudio de las diferentes opciones que ofrece para la realización de diseños, ya sean lógicos o físicos. Además del estudio de todas las posibilidades que ofrece el entorno, el trabajo se focalizó en la detección y comparación de las distintas opciones que ofrece para realizar una misma tarea, como ocurre con la asignación de pines o con la revisión de los resultados de una simulación, entre otras. Entrelazado con el estudio de las opciones que ofrece el entorno, se realizó el estudio de las distintas herramientas de trabajo integradas en el mismo. Una vez estudiado el entorno y las herramientas, se procedió a la realización del tutorial. Se capturaron todas las imágenes que se consideraron apropiadas para que al alumno le resultase cómodo y fácil seguir todas las indicaciones que el tutorial ofrece, para la realización de un ciclo de diseño lógico completo. Tras la realización del tutorial, se procedió a revisar la amplia documentación que el fabricante ofrece de cada una de las distintas familias de dispositivos que fabrica. El fin de esta revisión no fue otro que realizar una caracterización de las distintas familias, que pudiera servir de apoyo a la hora de elegir un dispositivo de este fabricante para la realización de un determinado diseño. Este estudio de las familias de dispositivos del fabricante, también se realizó para detectar qué familia de dispositivos era la más idónea para incluir uno de sus miembros en una hipotética placa de prototipado, para la realización de prácticas de laboratorio. ABSTRACT. This project consists in the analysis of the characteristics and the design cycle associated with the IspLEVER environment of CAD, by Lattice Semiconductor. The objective of that analysis is to evaluate their suitability for teaching engineering related to wired digital systems. Based on this analysis a guide was made for managing the different tools that are integrated into the environment. In addition, the characterization of several families by the manufacturer Lattice Semiconductor was made, with the objective that it could be used to support the choice of a Lattice’s device to perform a certain design. To start the IspLEVER environment and tools study, I began with a familiarization with the environment. This familiarization consisted in a study of the manufacturer documentation offered in their web page, http://www.latticesemi.com. After that, I had a general view about the characteristics of the environment and environment tools. Then I continued downloading the installation package. The manufacturer offers an evaluation version that expires in the period of one year. After that download, the environment was installed. Finally, the licensing procedure was followed to finish with the preparations. Then, the software was prepared for its utilization. Following, several work hours were wasted without documentation, trying to create designs. This work has been to identify how intuitive the environment is when you have knowledge of electronic CAD tools. After this first point of contact with the real environment, I proceeded to study different offered options, by the manufacturer, for the realization of either logical or physical designs. In addition to studying all the possibilities offered by the environment, the work is focused on the detection and comparison of the various options offered to perform the same task, as with the pin assignment or reviewing the results of a simulation… At the same time, the environment tools were studied. At this point, I began creating the tutorial. I captured all the figures that I consider important to make it easy to the students. The tutorial contains a complete logical design cycle. When the tutorial was finished, I started to review the manufacturer documentation about each devices family. The purpose of this review was to characterize the different families to support the device selection in future designs. Another purpose of that characterization was focused on the detection of the best family to include one of its members in a prototyping board for conducting laboratory practices.

Computer-Aided Business Model Design

There is a lack of dedicated tools for business model design at a strategic level. However, in today's economic world the need to be able to quickly reinvent a company's business model is essential to stay competitive. This research focused on identifying the functionalities that are necessary in a computer-aided design (CAD) tool for the design of business models in a strategic context. Using design science research methodology a series of techniques and prototypes have been designed and evaluated to offer solutions to the problem. The work is a collection of articles which can be grouped into three parts: First establishing the context of how the Business Model Canvas (BMC) is used to design business models and explore the way in which CAD can contribute to the design activity. The second part extends on this by proposing new technics and tools which support elicitation, evaluation (assessment) and evolution of business models design with CAD. This includes features such as multi-color tagging to easily connect elements, rules to validate coherence of business models and features that are adapted to the correct business model proficiency level of its users. A new way to describe and visualize multiple versions of a business model and thereby help in addressing the business model as a dynamic object was also researched. The third part explores extensions to the business model canvas such as an intermediary model which helps IT alignment by connecting business model and enterprise architecture. And a business model pattern for privacy in a mobile environment, using privacy as a key value proposition. The prototyped techniques and proposition for using CAD tools in business model modeling will allow commercial CAD developers to create tools that are better suited to the needs of practitioners.

XML-based information management environment for PE technologies

Printed electronics is an emerging concept in electronics manufacturing and it is in very early development stage. The technology is not stable, design kits are not developed, and flows and Computer Aided Design (CAD) tools are not fixed yet. The European project TDK4PE addresses all this issues and this PFC has been realized on this context. The goal is to develop an XML-based information system for the collection and management of information from the technology and cell libraries developed in TDK4PE. This system will ease the treatment of that information for a later generation of specific Design Kits (DK) and the corresponding documentation. This work proposes a web application to generate technology files and design kits in a formatted way; it also proposes a structure for them and a database implementation for storing the needed information. The application will allow its users to redefine the structure of those files, as well as export and import XML files, between other formats.

Business model design: an evaluation of paper-based and computer-aided canvases

In recent years, Business Model Canvas design has evolved from being a paper-based activity to one that involves the use of dedicated computer-aided business model design tools. We propose a set of guidelines to help design more coherent business models. When combined with functionalities offered by CAD tools, they show great potential to improve business model design as an ongoing activity. However, in order to create complex solutions, it is necessary to compare basic business model design tasks, using a CAD system over its paper-based counterpart. To this end, we carried out an experiment to measure user perceptions of both solutions. Performance was evaluated by applying our guidelines to both solutions and then carrying out a comparison of business model designs. Although CAD did not outperform paper-based design, the results are very encouraging for the future of computer-aided business model design.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Methodology analysis of a computational tool used in electronic circuit design

This paper considers the importance of using a top-down methodology and suitable CAD tools in the development of electronic circuits. The paper presents an evaluation of the methodology used in a computational tool created to support the synthesis of digital to analog converter models by translating between different tools used in a wide variety of applications. This tool is named MS 2SV and works directly with the following two commercial tools: MATLAB/Simulink and SystemVision. Model translation of an electronic circuit is achieved by translating a mixed-signal block diagram developed in Simulink into a lower level of abstraction in VHDL-AMS and the simulation project support structure in SystemVision. The method validation was performed by analyzing the power spectral of the signal obtained by the discrete Fourier transform of a digital to analog converter simulation model. © 2011 IEEE.

Models and methods for power monolithic microwave integrated circuits

Computer aided design of Monolithic Microwave Integrated Circuits (MMICs) depends critically on active device models that are accurate, computationally efficient, and easily extracted from measurements or device simulators. Empirical models of active electron devices, which are based on actual device measurements, do not provide a detailed description of the electron device physics. However they are numerically efficient and quite accurate. These characteristics make them very suitable for MMIC design in the framework of commercially available CAD tools. In the empirical model formulation it is very important to separate linear memory effects (parasitic effects) from the nonlinear effects (intrinsic effects). Thus an empirical active device model is generally described by an extrinsic linear part which accounts for the parasitic passive structures connecting the nonlinear intrinsic electron device to the external world. An important task circuit designers deal with is evaluating the ultimate potential of a device for specific applications. In fact once the technology has been selected, the designer would choose the best device for the particular application and the best device for the different blocks composing the overall MMIC. Thus in order to accurately reproducing the behaviour of different-in-size devices, good scalability properties of the model are necessarily required. Another important aspect of empirical modelling of electron devices is the mathematical (or equivalent circuit) description of the nonlinearities inherently associated with the intrinsic device. Once the model has been defined, the proper measurements for the characterization of the device are performed in order to identify the model. Hence, the correct measurement of the device nonlinear characteristics (in the device characterization phase) and their reconstruction (in the identification or even simulation phase) are two of the more important aspects of empirical modelling. This thesis presents an original contribution to nonlinear electron device empirical modelling treating the issues of model scalability and reconstruction of the device nonlinear characteristics. The scalability of an empirical model strictly depends on the scalability of the linear extrinsic parasitic network, which should possibly maintain the link between technological process parameters and the corresponding device electrical response. Since lumped parasitic networks, together with simple linear scaling rules, cannot provide accurate scalable models, either complicate technology-dependent scaling rules or computationally inefficient distributed models are available in literature. This thesis shows how the above mentioned problems can be avoided through the use of commercially available electromagnetic (EM) simulators. They enable the actual device geometry and material stratification, as well as losses in the dielectrics and electrodes, to be taken into account for any given device structure and size, providing an accurate description of the parasitic effects which occur in the device passive structure. It is shown how the electron device behaviour can be described as an equivalent two-port intrinsic nonlinear block connected to a linear distributed four-port passive parasitic network, which is identified by means of the EM simulation of the device layout, allowing for better frequency extrapolation and scalability properties than conventional empirical models. Concerning the issue of the reconstruction of the nonlinear electron device characteristics, a data approximation algorithm has been developed for the exploitation in the framework of empirical table look-up nonlinear models. Such an approach is based on the strong analogy between timedomain signal reconstruction from a set of samples and the continuous approximation of device nonlinear characteristics on the basis of a finite grid of measurements. According to this criterion, nonlinear empirical device modelling can be carried out by using, in the sampled voltage domain, typical methods of the time-domain sampling theory.

Hybrid Methods for Resource Allocation and Scheduling Problems in Deterministic and Stochastic Environments

This work presents exact, hybrid algorithms for mixed resource Allocation and Scheduling problems; in general terms, those consist into assigning over time finite capacity resources to a set of precedence connected activities. The proposed methods have broad applicability, but are mainly motivated by applications in the field of Embedded System Design. In particular, high-performance embedded computing recently witnessed the shift from single CPU platforms with application-specific accelerators to programmable Multi Processor Systems-on-Chip (MPSoCs). Those allow higher flexibility, real time performance and low energy consumption, but the programmer must be able to effectively exploit the platform parallelism. This raises interest in the development of algorithmic techniques to be embedded in CAD tools; in particular, given a specific application and platform, the objective if to perform optimal allocation of hardware resources and to compute an execution schedule. On this regard, since embedded systems tend to run the same set of applications for their entire lifetime, off-line, exact optimization approaches are particularly appealing. Quite surprisingly, the use of exact algorithms has not been well investigated so far; this is in part motivated by the complexity of integrated allocation and scheduling, setting tough challenges for ``pure'' combinatorial methods. The use of hybrid CP/OR approaches presents the opportunity to exploit mutual advantages of different methods, while compensating for their weaknesses. In this work, we consider in first instance an Allocation and Scheduling problem over the Cell BE processor by Sony, IBM and Toshiba; we propose three different solution methods, leveraging decomposition, cut generation and heuristic guided search. Next, we face Allocation and Scheduling of so-called Conditional Task Graphs, explicitly accounting for branches with outcome not known at design time; we extend the CP scheduling framework to effectively deal with the introduced stochastic elements. Finally, we address Allocation and Scheduling with uncertain, bounded execution times, via conflict based tree search; we introduce a simple and flexible time model to take into account duration variability and provide an efficient conflict detection method. The proposed approaches achieve good results on practical size problem, thus demonstrating the use of exact approaches for system design is feasible. Furthermore, the developed techniques bring significant contributions to combinatorial optimization methods.

Analog Signal Acquisition and Conditioning for Near-Field Capacitive Communication and Active Combined EEG-EIT Monitoring

The work of the present thesis is focused on the implementation of microelectronic voltage sensing devices, with the purpose of transmitting and extracting analog information between devices of different nature at short distances or upon contact. Initally, chip-to-chip communication has been studied, and circuitry for 3D capacitive coupling has been implemented. Such circuits allow the communication between dies fabricated in different technologies. Due to their novelty, they are not standardized and currently not supported by standard CAD tools. In order to overcome such burden, a novel approach for the characterization of such communicating links has been proposed. This results in shorter design times and increased accuracy. Communication between an integrated circuit (IC) and a probe card has been extensively studied as well. Today wafer probing is a costly test procedure with many drawbacks, which could be overcome by a different communication approach such as capacitive coupling. For this reason wireless wafer probing has been investigated as an alternative approach to standard on-contact wafer probing. Interfaces between integrated circuits and biological systems have also been investigated. Active electrodes for simultaneous electroencephalography (EEG) and electrical impedance tomography (EIT) have been implemented for the first time in a 0.35 um process. Number of wires has been minimized by sharing the analog outputs and supply on a single wire, thus implementing electrodes that require only 4 wires for their operation. Minimization of wires reduces the cable weight and thus limits the patient's discomfort. The physical channel for communication between an IC and a biological medium is represented by the electrode itself. As this is a very crucial point for biopotential acquisitions, large efforts have been carried in order to investigate the different electrode technologies and geometries and an electromagnetic model is presented in order to characterize the properties of the electrode to skin interface.

New designs of the ceramic bricks of horizontal hexagonal hollow

This article is intended to state that Technical Drawing is a multiple tool of expression and communication essential to develop inquiry processes, the scientifically basis and comprehension of drawings and technological designs that can be manufactured. We demonstrate graphically and analytically that spatial vision and graphic thinking allow us to identify graphically real life problems, develop proposals of solutions to be analysed from different points of view, plan and develop the project, provide information needed to make decisions on objects and technological processes. From the knowledge of Technical Drawing and CAD tools we have developed graphic analyses to improve and optimize our proposed modification of the geometry of the rectangular cells of conventional bricks by hexagonal cells, which is protected by a Spanish patent owned by the Polytechnic University of Madrid. This new internal geometry of the bricks will improve the efficiency and the acoustic damping of walls built with the ceramic bricks of horizontal hollow, maintaining the same size of the conventional bricks, without increasing costs either in the manufacture and the sale. A single brick will achieve the width equivalent to more than FOUR conventional bricks.

Desenvolvimento teórico e experimental de FSS com elementos fractais de Gosper em estruturas de multicamadas

The fractal self-similarity property is studied to develop frequency selective surfaces (FSS) with several rejection bands. Particularly, Gosper fractal curves are used to define the shapes of the FSS elements. Due to the difficulty of making the FSS element details, the analysis is developed for elements with up to three fractal levels. The simulation was carried out using Ansoft Designer software. For results validation, several FSS prototypes with fractal elements were fabricated. In the fabrication process, fractals elements were designed using computer aided design (CAD) tools. The prototypes were measured using a network analyzer (N3250A model, Agilent Technologies). Matlab software was used to generate compare measured and simulated results. The use of fractal elements in the FSS structures showed that the use of high fractal levels can reduce the size of the elements, at the same time as decreases the bandwidth. We also investigated the effect produced by cascading FSS structures. The considered cascaded structures are composed of two FSSs separated by a dielectric layer, which distance is varied to determine the effect produced on the bandwidth of the coupled geometry. Particularly, two FSS structures were coupled through dielectric layers of air and fiberglass. For comparison of results, we designed, fabricated and measured several prototypes of FSS on isolated and coupled structures. Agreement was observed between simulated and measured results. It was also observed that the use of cascaded FSS structures increases the FSSs bandwidths and, in particular cases, the number of resonant frequencies, in the considered frequency range. In future works, we will investigate the effects of using different types of fractal elements, in isolated, multilayer and coupled FSS structures for applications on planar filters, high-gain microstrip antennas and microwave absorbers