Synchronisation in high-performance integrated circuits

A distribui ção de um sinal relógio, com elevada precisão espacial (baixo skew) e temporal (baixo jitter ), em sistemas sí ncronos de alta velocidade tem-se revelado uma tarefa cada vez mais demorada e complexa devido ao escalonamento da tecnologia. Com a diminuição das dimensões dos dispositivos e a integração crescente de mais funcionalidades nos Circuitos Integrados (CIs), a precisão associada as transições do sinal de relógio tem sido cada vez mais afectada por varia ções de processo, tensão e temperatura. Esta tese aborda o problema da incerteza de rel ogio em CIs de alta velocidade, com o objetivo de determinar os limites do paradigma de desenho sí ncrono. Na prossecu ção deste objectivo principal, esta tese propõe quatro novos modelos de incerteza com âmbitos de aplicação diferentes. O primeiro modelo permite estimar a incerteza introduzida por um inversor est atico CMOS, com base em parâmetros simples e su cientemente gen éricos para que possa ser usado na previsão das limitações temporais de circuitos mais complexos, mesmo na fase inicial do projeto. O segundo modelo, permite estimar a incerteza em repetidores com liga ções RC e assim otimizar o dimensionamento da rede de distribui ção de relógio, com baixo esfor ço computacional. O terceiro modelo permite estimar a acumula ção de incerteza em cascatas de repetidores. Uma vez que este modelo tem em considera ção a correla ção entre fontes de ruí do, e especialmente util para promover t ecnicas de distribui ção de rel ogio e de alimentação que possam minimizar a acumulação de incerteza. O quarto modelo permite estimar a incerteza temporal em sistemas com m ultiplos dom ínios de sincronismo. Este modelo pode ser facilmente incorporado numa ferramenta autom atica para determinar a melhor topologia para uma determinada aplicação ou para avaliar a tolerância do sistema ao ru ído de alimentação. Finalmente, usando os modelos propostos, são discutidas as tendências da precisão de rel ogio. Conclui-se que os limites da precisão do rel ogio são, em ultima an alise, impostos por fontes de varia ção dinâmica que se preveem crescentes na actual l ogica de escalonamento dos dispositivos. Assim sendo, esta tese defende a procura de solu ções em outros ní veis de abstração, que não apenas o ní vel f sico, que possam contribuir para o aumento de desempenho dos CIs e que tenham um menor impacto nos pressupostos do paradigma de desenho sí ncrono.

Differential mixer with NMOS/PMOS stack at switching stage

This paper proposes a novel differential mixer topology. The traditional stage of switching is replaced by a stack of NMOS and PMOS transistors combined. A design is given of a 900 MHz down-conversion mixer using a 0.35 μm CMOS process. Comparison with conventional mixer shows that the topology leads to a better performance in terms of conversion gain and linearity. ©2012 IEEE.

Hysteresis modulation of multilevel inverters

The hysteresis modulation for power electronic converters is attractive in many different applications because of its unmatched dynamic response and wide command-tracking bandwidth. Its application and beneftis for two-level converters are well understood, but the extension of this strategy to multilevel converters is still under development. This paper summarizes and reviews the various hysteresis modulation approaches available in the literature for multilevel converters. The pros and cons of various techniques are described and compared for tracking the reference signal in order to attain an adequate switching optimization, excellent dynamic responses and high accuracy in steady-state operation. By using the recently developed multilevel hysteresis modulation approaches the advantages of using several accessible dc potentials in a multilevel inverter has been fully exploited. All of these hysteresis modulation approaches are testing for tracking a current reference when applied to a fivelevel inveter. The relevant simulation and experimental result are also presented. This study will provide a useful framweork and point of reference for the future development of hysteresis modulation for multilevel converters.

Distribution feeder voltage support and power factor control by distributed multiple inverters

The potential of distributed reactive power control to improve the voltage profile of radial distribution feeders has been reported in literature by few authors. However, the multiple inverters injecting or absorbing reactive power across a distribution feeder may introduce control interactions and/or voltage instability. Such controller interactions can be alleviated if the inverters are allowed to operate on voltage droop. First, the paper demonstrates that a linear shallow droop line can maintain the steady state voltage profile close to reference, up to a certain level of loading. Then, impacts of the shallow droop line control on line losses and line power factors are examined. Finally, a piecewise linear droop line which can achieve reduced line losses and close to unity power factor at the feeder source is proposed.

Harmonic quality of multilevel cascade inverters with random carrier phase pulse width modulation

The output harmonic quality of N series connected full-bridge dc-ac inverters is investigated. The inverters are pulse width modulated using a common reference signal but randomly phased carrier signals. Through analysis and simulation, probability distributions for inverter output harmonics and vector representations of N carrier phases are combined and assessed. It is concluded that a low total harmonic distortion is most likely to occur and will decrease further as N increases.

Harmonic quality of multilevel cascade inverters with random carrier phase pulse width modulation

The output harmonic quality of N series connected full-bridge dc-ac inverters is investigated. The inverters are pulse width modulated using a common reference signal but randomly phased carrier signals. Through analysis and simulation, probability distributions for inverter output harmonics and vector representations of N carrier phases are combined and assessed. It is concluded that a low total harmonic distortion is most likely to occur and will decrease further as N increases.

Robust control algorithm for grid-interfaced three-phase inverters with high-bandwidth LCL filter

The paper introduces the design of robust current and voltage control algorithms for a grid-connected three-phase inverter which is interfaced to the grid through a high-bandwidth three-phase LCL filter. The algorithms are based on the state feedback control which have been designed in a systematic approach and improved by using oversampling to deal with the issues arising due to the high-bandwidth filter. An adaptive loop delay compensation method has also been adopted to minimize the adverse effects of loop delay in digital controller and to increase the robustness of the control algorithm in the presence of parameter variations. Simulation results are presented to validate the effectiveness of the proposed algorithm.

Effectiveness of reactive power capability of photo voltaic inverters to maintain voltage profile in a residential distribution feeder

Large penetration of rooftop PVs has resulted in unacceptable voltage profile in many residential distribution feeders. Limiting real power injection from PVs to alleviate over voltage problem is not feasible due to loss of green power and hence corresponding revenue loss. Reactive capability of the PV inverter can be a solution to address over voltage and voltage dip problems to some extent. This paper proposes an algorithm to utilize reactive capability of PV inverters and investigate their effectiveness for voltage improvement based on R/X ratio of the feeder. The length and loading level of the feeder for a particular R/X ratio to have acceptable voltage profile is also investigated. This can be useful for suburban design and residential distribution planning. Furthermore, coordination among different PVs using residential smart meters via a substation based controller is also proposed.

Effectiveness of reactive power capability of photo voltaic inverters to maintain acceptable voltage profile in a residential distribution system

Integration of rooftop PVs and increasing peak demand in the residential distribution networks has resulted in unacceptable voltage profile. Curtailing PV generation to alleviate overvoltage problem and making regular network investment to cater peak demand is not always feasible. Reactive capability of the PV inverter can be a solution to address voltage dip and over voltage problems to some extent. This paper proposes an algorithm to utilize reactive capability of PV inverters and investigate their effectiveness on feeder length and R/X ratio of the line. Feeder loading level for a particular R/X ratio to have acceptable voltage profile is also investigated. Furthermore, the need of appropriate feeder distances and R/X ratio for acceptable voltage profile, which can be useful for suburban design and distribution planning, is explored.

Five-level current-source inverters with buck-boost and inductive-current balancing capabilities

This paper presents new five-level current-source inverters (CSIs) with voltage/current buck-boost capability, unlike existing five-level CSIs where only voltage-boost operation is supported. The proposed inverters attain self-inductive-current-balancing per switching cycle at their dc front ends without having to include additional balancing hardware or complex control manipulation. The inverters can conveniently be controlled by using the well-established phase-shifted carrier modulation scheme with only two additional linear references and a mapping logic table needed. Existing modulators can therefore be conveniently retrofitted for controlling the presented inverters. By appropriately coordinating the inverter gating signals, their implementations can be realized by using the least number of components without degrading performance. These enhanced features of the inverters have already been verified in simulation and experimentally using a scaled-down laboratory platform.