Organic functionalisation, doping and characterisation of semiconductor surfaces for future CMOS device applications

Organic Functionalisation, Doping and Characterisation of Semiconductor Surfaces for Future CMOS Device Applications Semiconductor materials have long been the driving force for the advancement of technology since their inception in the mid-20th century. Traditionally, micro-electronic devices based upon these materials have scaled down in size and doubled in transistor density in accordance with the well-known Moore’s law, enabling consumer products with outstanding computational power at lower costs and with smaller footprints. According to the International Technology Roadmap for Semiconductors (ITRS), the scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) is proceeding at a rapid pace and will reach sub-10 nm dimensions in the coming years. This scaling presents many challenges, not only in terms of metrology but also in terms of the material preparation especially with respect to doping, leading to the moniker “More-than-Moore”. Current transistor technologies are based on the use of semiconductor junctions formed by the introduction of dopant atoms into the material using various methodologies and at device sizes below 10 nm, high concentration gradients become a necessity. Doping, the controlled and purposeful addition of impurities to a semiconductor, is one of the most important steps in the material preparation with uniform and confined doping to form ultra-shallow junctions at source and drain extension regions being one of the key enablers for the continued scaling of devices. Monolayer doping has shown promise to satisfy the need to conformally dope at such small feature sizes. Monolayer doping (MLD) has been shown to satisfy the requirements for extended defect-free, conformal and controllable doping on many materials ranging from the traditional silicon and germanium devices to emerging replacement materials such as III-V compounds This thesis aims to investigate the potential of monolayer doping to complement or replace conventional doping technologies currently in use in CMOS fabrication facilities across the world.

A low-voltage wide-swing programmable-gain current amplifier

A CMOS low-voltage, wide-swing continuous-time current amplifier is presented. Exhibiting an open-loop architecture, the circuit is composed of transresistance and transconductance stages built upon triode-operating transistors. In addition to an extended dynamic range, the current gain can be programmed within good accuracy by a rapport involving only transistor geometries and tuning biases. Low temperature-drift on gain setting is then expected.In accordance with a 0.35 mum n-well CMOS fabrication process and a single 1.1 V-supply, a balanced current-amplifier is designed for a programmable gain-range of 6 - 34 dB and optimized with respect to dynamic range. Simulated results from PSPICE and Bsim3v3 models indicate, for a 100 muA(pp)-output current, a THD of 0.96 and 1.87% at 1 KHz and 100 KHz, respectively. Input noise is 120 pArootHz @ 10 Hz, with S/N = 63.2 dB @ 1%-THD. At maximum gain, total quiescent consumption is 334 muW. Measurements from a prototyped amplifier reveal a gain-interval of 4.8-33.1 dB and a maximum current swing of 120 muA(pp). The current-amplifier bandwidth is above 1 MHz.

An accurate low-voltage analog memory-cell with built-in multiplication

A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.

A Gm-C bump equalizer for low-voltage low-power applications

A low-voltage low-power 2nd-order CMOS pseudo-differential bump-equalizer is presented. Its topology comprises a bandpass section with adjustable center frequency and quality factor, together with a programmable current amplifier. The basic building blocks are triode-operating transconductors, tunable by means of either a DC voltage or a digitally controlled current divider. The bump-equalizer as part of a battery-operated hearing aid device is designed for a 1.4V-supply and a 0.35μm CMOS fabrication process. The circuit performance is supported by a set of simulation results, which indicates a center frequency from 600Hz to 2.4kHz, 1≤Q≤5, and an adjustable gain within ±6dB at center frequency. The filter dynamic range lies around 40dB. Quiescent consumption is kept below 12μW for any configuration of the filter.

Comparative study of the proton beam effects between the conventional and Circular-Gate MOSFETs

The study of ionizing radiation effects on semiconductor devices is of great relevance for the global technological development and is a necessity in some strategic areas in Brazil. This work presents preliminary results of radiation effects in MOSFETs that were exposed to 3.2 Grad radiation dose produced by a 2.6-MeV proton beam. The focus of this work was to electrically characterize a Rectangular-Gate MOSFET (RGT) and a Circular-Gate MOSFET (CGT), manufactured with the On Semiconductor 0.5 mu m standard CMOS fabrication process and to verify a suitable geometry for space applications. During the experiment, I-DS x V-GS curves were measured. After irradiation, the RGT off-state current (I-OFF) increased approximately two orders of magnitude reaching practically the same value of the I-OFF in the CGT, which only doubled its value. (C) 2011 Elsevier B.V. All rights reserved.

Post-CMOS compatible high-throughput fabrication of AIN-based piezoelectric microcantilevers

A post-complementary metal oxide semiconductor (CMOS) compatible microfabrication process of piezoelectric cantilevers has been developed. The fabrication process is suitable for standard silicon technology and provides low-cost and high-throughput manufacturing. This work reports design, fabrication and characterization of piezoelectric cantilevers based on aluminum nitride (AlN) thin films synthesized at room temperature. The proposed microcantilever system is a sandwich structure composed of chromium (Cr) electrodes and a sputtered AlN film. The key issue for cantilever fabrication is the growth at room temperature of the AlN layer by reactive sputtering, making possible the innovative compatibility of piezoelectric MEMS devices with CMOS circuits already processed. AlN and Cr have been etched by inductively coupled plasma (ICP) dry etching using a BCl3–Cl2–Ar plasma chemistry. As part of the novelty of the post-CMOS micromachining process presented here, a silicon Si (1 0 0) wafer has been used as substrate as well as the sacrificial layer used to release the microcantilevers. In order to achieve this, the Si surface underneath the structure has been wet etched using an HNA (hydrofluoric acid + nitric acid + acetic acid) based solution. X-ray diffraction (XRD) characterization indicated the high crystalline quality of the AlN film. An atomic force microscope (AFM) has been used to determine the Cr electrode surface roughness. The morphology of the fabricated devices has been studied by scanning electron microscope (SEM). The cantilevers have been piezoelectrically actuated and their out-of-plane vibration modes were detected by vibrometry.

A CMOS/SOI single-input PWM discriminator for low-voltage body-implanted applications

A CMOS/SOI circuit to decode Pulse-Width Modulation (PWM) signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a novel double-integration concept and does not require low-pass filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 mum single-metal thin-film CMOS/SOI fabrication process and has an effective area of 2 mm(2). Measured resolution of encoding parameter a is better than 10% at 6 MHz and V-DD = 3.3 V. Idle-mode consumption is 340 LW. Pulses of frequencies up to 15 MHz and alpha = 10% can be discriminated for 2.3 V less than or equal to V-DD less than or equal to 3.3 V. Such an excellent immunity to V-DD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

Integration of room temperature single electron transistor with CMOS subsystem

The single electron transistor (SET) is a charge-based device that may complement the dominant metal-oxide-semiconductor field effect transistor (MOSFET) technology. As the cost of scaling MOSFET to smaller dimensions are rising and the the basic functionality of MOSFET is encountering numerous challenges at dimensions smaller than 10nm, the SET has shown the potential to become the next generation device which operates based on the tunneling of electrons. Since the electron transfer mechanism of a SET device is based on the non-dissipative electron tunneling effect, the power consumption of a SET device is extremely low, estimated to be on the order of 10^-18J. The objectives of this research are to demonstrate technologies that would enable the mass produce of SET devices that are operational at room temperature and to integrate these devices on top of an active complementary-MOSFET (CMOS) substrate. To achieve these goals, two fabrication techniques are considered in this work. The Focus Ion Beam (FIB) technique is used to fabricate the islands and the tunnel junctions of the SET device. A Ultra-Violet (UV) light based Nano-Imprint Lithography (NIL) call Step-and-Flash- Imprint Lithography (SFIL) is used to fabricate the interconnections of the SET devices. Combining these two techniques, a full array of SET devices are fabricated on a planar substrate. Test and characterization of the SET devices has shown consistent Coulomb blockade effect, an important single electron characteristic. To realize a room temperature operational SET device that function as a logic device to work along CMOS, it is important to know the device behavior at different temperatures. Based on the theory developed for a single island SET device, a thermal analysis is carried out on the multi-island SET device and the observation of changes in Coulomb blockade effect is presented. The results show that the multi-island SET device operation highly depends on temperature. The important parameters that determine the SET operation is the effective capacitance Ceff and tunneling resistance Rt . These two parameters lead to the tunneling rate of an electron in the SET device, Γ. To obtain an accurate model for SET operation, the effects of the deviation in dimensions, the trap states in the insulation, and the background charge effect have to be taken into consideration. The theoretical and experimental evidence for these non-ideal effects are presented in this work.

A 0.0016 mm(2) 0.64 nJ leakage-based CMOS temperature sensor

This paper presents a CMOS temperature sensor based on the thermal dependencies of the leakage currents targeting the 65 nm node. To compensate for the effect of process fluctuations, the proposed sensor realizes the ratio of two measures of the time it takes a capacitor to discharge through a transistor in the subthreshold regime. Furthermore, a novel charging mechanism for the capacitor is proposed to further increase the robustness against fabrication variability. The sensor, including digitization and interfacing, occupies 0.0016 mm2 and has an energy consumption of 47.7–633 pJ per sample. The resolution of the sensor is 0.28 °C, and the 3σ inaccuracy over the range 40–110 °C is 1.17 °C.

CMOS integration of AlN based piezoelectric microcantilevers

El gran crecimiento de los sistemas MEMS (Micro Electro Mechanical Systems) así como su presencia en la mayoría de los dispositivos que usamos diariamente despertó nuestro interés. Paralelamente, la tecnología CMOS (Complementary Metal Oxide Semiconductor) es la tecnología más utilizada para la fabricación de circuitos integrados. Además de ventajas relacionadas con el funcionamiento electrónico del dispositivo final, la integración de sistemas MEMS en la tecnología CMOS reduce significantemente los costes de fabricación. Algunos de los dispositivos MEMS con mayor variedad de aplicaciones son los microflejes. Estos dispositivos pueden ser utilizados para la extracción de energía, en microscopios de fuerza atómica o en sensores, como por ejemplo, para biodetección. Los materiales piezoeléctricos más comúnmente utilizados en aplicaciones MEMS se sintetizan a altas temperaturas y por lo tanto no son compatibles con la tecnología CMOS. En nuestro caso hemos usado nitruro de alumino (AlN), que se deposita a temperatura ambiente y es compatible con la tecnología CMOS. Además, es biocompatible, y por tanto podría formar parte de un dispositivo que actúe como biosensor. A lo largo de esta tesis hemos prestado especial atención en desarrollar un proceso de fabricación rápido, reproducible y de bajo coste. Para ello, todos los pasos de fabricación han sido minuciosamente optimizados. Los parámetros de sputtering para depositar el AlN, las distintas técnicas y recetas de ataque, los materiales que actúan como electrodos o las capas sacrificiales para liberar los flejes son algunos de los factores clave estudiados en este trabajo. Una vez que la fabricación de los microflejes de AlN ha sido optimizada, fueron medidos para caracterizar sus propiedades piezoeléctricas y finalmente verificar positivamente su viabilidad como dispositivos piezoeléctricos. ABSTRACT The huge growth of MEMS (Micro Electro Mechanical Systems) as well as their presence in most of our daily used devices aroused our interest on them. At the same time, CMOS (Complementary Metal Oxide Semiconductor) technology is the most popular technology for integrated circuits. In addition to advantages related with the electronics operation of the final device, the integration of MEMS with CMOS technology reduces the manufacturing costs significantly. Some of the MEMS devices with a wider variety of applications are the microcantilevers. These devices can be used for energy harvesting, in an atomic force microscopes or as sensors, as for example, for biodetection. Most of the piezoelectric materials used for these MEMS applications are synthesized at high temperature and consequently are not compatible with CMOS technology. In our case we have used aluminum nitride (AlN), which is deposited at room temperature and hence fully compatible with CMOS technology. Otherwise, it is biocompatible and and can be used to compose a biosensing device. During this thesis work we have specially focused our attention in developing a high throughput, reproducible and low cost fabrication process. All the manufacturing process steps of have been thoroughly optimized in order to achieve this goal. Sputtering parameters to synthesize AlN, different techniques and etching recipes, electrode material and sacrificial layers are some of the key factors studied in this work to develop the manufacturing process. Once the AlN microcantilevers fabrication was optimized, they were measured to characterize their piezoelectric properties and to successfully check their viability as piezoelectric devices.

Noise and PSRR improvement technique for TPC readout front-end in CMOS. technology.

ALICE is one of four major experiments of particle accelerator LHC installed in the European laboratory CERN. The management committee of the LHC accelerator has just approved a program update for this experiment. Among the upgrades planned for the coming years of the ALICE experiment is to improve the resolution and tracking efficiency maintaining the excellent particles identification ability, and to increase the read-out event rate to 100 KHz. In order to achieve this, it is necessary to update the Time Projection Chamber detector (TPC) and Muon tracking (MCH) detector modifying the read-out electronics, which is not suitable for this migration. To overcome this limitation the design, fabrication and experimental test of new ASIC named SAMPA has been proposed . This ASIC will support both positive and negative polarities, with 32 channels per chip and continuous data readout with smaller power consumption than the previous versions. This work aims to design, fabrication and experimental test of a readout front-end in 130nm CMOS technology with configurable polarity (positive/negative), peaking time and sensitivity. The new SAMPA ASIC can be used in both chambers (TPC and MCH). The proposed front-end is composed of a Charge Sensitive Amplifier (CSA) and a Semi-Gaussian shaper. In order to obtain an ASIC integrating 32 channels per chip, the design of the proposed front-end requires small area and low power consumption, but at the same time requires low noise. In this sense, a new Noise and PSRR (Power Supply Rejection Ratio) improvement technique for the CSA design without power and area impact is proposed in this work. The analysis and equations of the proposed circuit are presented which were verified by electrical simulations and experimental test of a produced chip with 5 channels of the designed front-end. The measured equivalent noise charge was <550e for 30mV/fC of sensitivity at a input capacitance of 18.5pF. The total core area of the front-end was 2300?m × 150?m, and the measured total power consumption was 9.1mW per channel.

High-Performance WSe2 CMOS Technology and Integrated Circuits.

Because of their extraordinary structural and electrical properties, two dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (~38) and small static power (Pico-Watts), paving the way for low power electronic system in 2D materials.

Conception, caractérisation et optimisation de SPAD en technologie Dalsa HV CMOS 0.8 μm pour intégration dans un 3D-SiPM

Résumé : Les photodiodes à avalanche monophotonique (SPAD) sont d'intérêts pour les applications requérant la détection de photons uniques avec une grande résolution temporelle, comme en physique des hautes énergies et en imagerie médicale. En fait, les matrices de SPAD, souvent appelés photomultiplicateurs sur silicium (SiPM), remplacent graduellement les tubes photomultiplicateurs (PMT) et les photodiodes à avalanche (APD). De plus, il y a une tendance à utiliser les matrices de SPAD en technologie CMOS afin d'obtenir des pixels intelligents optimisés pour la résolution temporelle. La fabrication de SPAD en technologie CMOS commerciale apporte plusieurs avantages par rapport aux procédés optoélectroniques comme le faible coût, la capacité de production, l'intégration d'électronique et la miniaturisation des systèmes. Cependant, le défaut principal du CMOS est le manque de flexibilité de conception au niveau de l'architecture du SPAD, causé par le caractère fixe et standardisé des étapes de fabrication en technologie CMOS. Un autre inconvénient des matrices de SPAD CMOS est la perte de surface photosensible amenée par la présence de circuits CMOS. Ce document présente la conception, la caractérisation et l'optimisation de SPAD fabriqués dans une technologie CMOS commerciale (Teledyne DALSA 0.8µm HV CMOS - TDSI CMOSP8G). Des modifications de procédé sur mesure ont été introduites en collaboration avec l'entreprise CMOS pour optimiser les SPAD tout en gardant la compatibilité CMOS. Les matrices de SPAD produites sont dédiées à être intégrées en 3D avec de l'électronique CMOS économique (TDSI) ou avec de l'électronique CMOS submicronique avancée, produisant ainsi un SiPM 3D numérique. Ce SiPM 3D innovateur vise à remplacer les PMT, les APD et les SiPM commerciaux dans les applications à haute résolution temporelle. L'objectif principal du groupe de recherche est de développer un SiPM 3D avec une résolution temporelle de 10 ps pour usage en physique des hautes énergies et en imagerie médicale. Ces applications demandent des procédés fiables avec une capacité de production certifiée, ce qui justifie la volonté de produire le SiPM 3D avec des technologies CMOS commerciales. Ce mémoire étudie la conception, la caractérisation et l'optimisation de SPAD fabriqués en technologie TDSI-CMOSP8G.

Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS

Résumé : Le transistor monoélectronique (SET) est un dispositif nanoélectronique très attractif à cause de son ultra-basse consommation d’énergie et sa forte densité d’intégration, mais il n’a pas les capacités suffisantes pour pouvoir remplacer complètement la technologie CMOS. Cependant, la combinaison de la technologie SET avec celle du CMOS est une voie intéressante puisqu’elle permet de profiter des forces de chacune, afin d’obtenir des circuits avec des fonctionnalités additionnelles et uniques. Cette thèse porte sur l’intégration 3D monolithique de nanodispositifs dans le back-end-of-line (BEOL) d’une puce CMOS. Cette approche permet d’obtenir des circuits hybrides et de donner une valeur ajoutée aux puces CMOS actuelles sans altérer le procédé de fabrication du niveau des transistors MOS. L’étude se base sur le procédé nanodamascène classique développé à l’UdeS qui a permis la fabrication de dispositifs nanoélectroniques sur un substrat de SiO2. Ce document présente les travaux réalisés sur l’optimisation du procédé de fabrication nanodamascène, afin de le rendre compatible avec le BEOL de circuits CMOS. Des procédés de gravure plasma adaptés à la fabrication de nanostructures métalliques et diélectriques sont ainsi développés. Le nouveau procédé nanodamascène inverse a permis de fabriquer des jonctions MIM et des SET métalliques sur une couche de SiO2. Les caractérisations électriques de MIM et de SET formés avec des jonctions TiN/Al2O3 ont permis de démontrer la présence de pièges dans les jonctions et la fonctionnalité d’un SET à basse température (1,5 K). Le transfert de ce procédé sur CMOS et le procédé d’interconnexions verticales sont aussi développés par la suite. Finalement, un circuit 3D composé d’un nanofil de titane connecté verticalement à un transistor MOS est réalisé et caractérisé avec succès. Les résultats obtenus lors de cette thèse permettent de valider la possibilité de co-intégrer verticalement des dispositifs nanoélectroniques avec une technologie CMOS, en utilisant un procédé de fabrication compatible.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.