A Comaparison Study of EM and Physical Equivalent Circuit Modeling for MIM CMOS Capacitors

In this Letter a new physical model for metal-insulatormetal CMOS capacitors is presented. In the model the parameters of the circuit are derived from the physical structural details. Physical behaviors due to metal skin effect and inductance have been considered. The model has been confirmed by 3D EM simulator and design rules proposed. The model presented is scalable with capacitor geometry, allowing designers to predict and optimize quality factor. The approach has been verified for MIM CMOS capacitors

High tuning range AlSi RF MEMS capacitors fabricated with sacrificial amorphous silicon surface micromachining

This paper reports the fabrication and electrical characterization of high tuning range AlSi RF MEMS capacitors. We present experimental results obtained by a surface micromachining process that uses dry etching of sacrificial amorphous silicon to release Al-1%Si membranes and has a low thermal budget (<450 °C) being compatible with CMOS post-processing. The proposed silicon sacrificial layer dry etching (SSLDE) process is able to provide very high Si etch rates (3-15 μm/min, depending on process parameters) with high Si: SiO2 selectivity (>10,000:1). Single- and double-air-gap MEMS capacitors, as well as some dedicated test structures needed to calibrate the electro-mechanical parameters and explore the reliability of the proposed technology, have been fabricated with the new process. S-parameter measurements from 100 MHz up to 2 GHz have shown a capacitance tuning range higher than 100% with the double-air-gap architecture. The tuning range can be enlarged with a proper DC electrical bias of the capacitor electrodes. Finally, the reported results make the proposed MEMS tuneable capacitor a good candidate for above-IC integration in communications applications. © 2004 Elsevier B.V. All rights reserved.

Circuit design and simulation of a CMOS-based preamplifier for brain neural signals

A novel CMOS-based preamplifier for amplifying brain neural signal obtained by scalp electrodes in brain-computer interface (BCI) is presented in this paper. By means of constructing effective equivalent input circuit structure of the preamplifier, two capacitors of 5 pF are included to realize the DC suppression compared to conventional preamplifiers. Then this preamplifier is designed and simulated using the standard 0.6 mu m MOS process technology model parameters with a supply voltage of 5 volts. With differential input structures adopted, simulation results of the preamplifier show that the input impedance amounts to more than 2 Gohm with brain neural signal frequency of 0.5 Hz-100 Hz. The equivalent input noise voltage is 18 nV/Hz(1/2). The common mode rejection ratio (CMRR) of 112 dB and the open-loop differential gain of 90 dB are achieved.

Simulation of a Monolithic Integrated CMOS Preamplifier for Neural Recordings

A monolithic integrated CMOS preamplifier is presented for neural recording applications. Two AC-coupied capacitors are used to eliminate the large and random DC offsets existing in the electrode-electrolyte interface. Diode-connected nMOS transistors with a negative voltage between the gate and source are candidates for the large resistors necessary for the preamplifier. A novel analysis is given to determine the noise power spectral density. Simulation results show that the two-stage CMOS preamplifier in a closed-loop capacitive feedback configuration provides an AC in-band gain of 38.8dB,a DC gain of 0,and an input-referred noise of 277nVmax, integrated from 0. 1Hz to 1kHz. The preamplifier can eliminate the DC offset voltage and has low input-referred noise by novel circuit configuration and theoretical analysis.

Ferroelectric hafnium oxide: A CMOS-compatible and highly scalable approach to future ferroelectric memories

With the ability to engineer ferroelectricity in HfO2 thin films, manufacturable and highly scaled MFM capacitors and MFIS-FETs can be implemented into a CMOS-environment. NVM properties of the resulting devices are discussed and contrasted to existing perovskite based FRAM.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

Optimal allocation and sizing of capacitors to minimize the transmission line loss and to improve the voltage profile

To allocate and size capacitors in a distribution system, an optimization algorithm, called Discrete Particle Swarm Optimization (DPSO), is employed in this paper. The objective is to minimize the transmission line loss cost plus capacitors cost. During the optimization procedure, the bus voltage, the feeder current and the reactive power flowing back to the source side should be maintained within standard levels. To validate the proposed method, the semi-urban distribution system that is connected to bus 2 of the Roy Billinton Test System (RBTS) is used. This 37-bus distribution system has 22 loads being located in the secondary side of a distribution substation (33/11 kV). Reducing the transmission line loss in a standard system, in which the transmission line loss consists of only about 6.6 percent of total power, the capabilities of the proposed technique are seen to be validated.

Optimal control of distributed generators and capacitors by hybrid DPSO

In this paper, a comprehensive planning methodology is proposed that can minimize the line loss, maximize the reliability and improve the voltage profile in a distribution network. The injected active and reactive power of Distributed Generators (DG) and the installed capacitor sizes at different buses and for different load levels are optimally controlled. The tap setting of HV/MV transformer along with the line and transformer upgrading is also included in the objective function. A hybrid optimization method, called Hybrid Discrete Particle Swarm Optimization (HDPSO), is introduced to solve this nonlinear and discrete optimization problem. The proposed HDPSO approach is a developed version of DPSO in which the diversity of the optimizing variables is increased using the genetic algorithm operators to avoid trapping in local minima. The objective function is composed of the investment cost of DGs, capacitors, distribution lines and HV/MV transformer, the line loss, and the reliability. All of these elements are converted into genuine dollars. Given this, a single-objective optimization method is sufficient. The bus voltage and the line current as constraints are satisfied during the optimization procedure. The IEEE 18-bus test system is modified and employed to evaluate the proposed algorithm. The results illustrate the unavoidable need for optimal control on the DG active and reactive power and capacitors in distribution networks.

A new technique for optimal allocation and sizing of capacitors and setting of LTC

An iterative based strategy is proposed for finding the optimal rating and location of fixed and switched capacitors in distribution networks. The substation Load Tap Changer tap is also set during this procedure. A Modified Discrete Particle Swarm Optimization is employed in the proposed strategy. The objective function is composed of the distribution line loss cost and the capacitors investment cost. The line loss is calculated using estimation of the load duration curve to multiple levels. The constraints are the bus voltage and the feeder current which should be maintained within their standard range. For validation of the proposed method, two case studies are tested. The first case study is the semi-urban 37-bus distribution system which is connected at bus 2 of the Roy Billinton Test System which is located in the secondary side of a 33/11 kV distribution substation. The second case is a 33 kV distribution network based on the modification of the 18-bus IEEE distribution system. The results are compared with prior publications to illustrate the accuracy of the proposed strategy.

An analysis on the possibility of using capacitors of a three-level capacitor clamped inverter as power smoothing elements for wind power systems

This paper presents a new direct integration scheme for supercapacitors that are used to mitigate short term power fluctuations in wind power systems. The idea is to replace ordinary capacitors of a 3-level flying capacitor inverter by supercapacitors and operate them under variable voltage conditions. This approach eliminates the need of interfacing dc-dc converters for supercapacitor integration and thus considerably improves the overall efficiency. However, the major problem of this unique system is the change of supercapacitor voltages. An analysis on the effects of these voltage variations are presented. A space vector modulation method, built from the scratch, is proposed to generate undistorted current even in the presence of dynamic changes in supercapacitor voltages. A supercapacitor voltage equalisation algorithm is also proposed. Furthermore, resistive behavior of supercapacitors at high frequencies and the need for a low pass filter are highlighted. Simulation results are presented to verify the efficacy of the proposed system in suppressing short term wind power fluctuations.

Hydrogel-polymer electrolytes for electrochemical capacitors: an overview

Electrochemical capacitors are electrochemical devices with fast and highly reversible charge-storage and discharge capabilities. The devices are attractive for energy storage particularly in applications involving high-power requirements. Electrochemical capacitors employ two electrodes and an aqueous or a non-aqueous electrolyte, either in liquid or solid form; the latter provides the advantages of compactness, reliability, freedom from leakage of any liquid component and a large operating potential-window. One of the classes of solid electrolytes used in capacitors is polymer-based and they generally consist of dry solid-polymer electrolytes or gel-polymer electrolyte or composite-polymer electrolytes. Dry solid-polymer electrolytes suffer from poor ionic-conductivity values, between 10(-8) and 10(-7) S cm(-1) under ambient conditions, but are safer than gel-polymer electrolytes that exhibit high conductivity of ca. 10(-3) S cm(-1) under ambient conditions. The aforesaid polymer-based electrolytes have the advantages of a wide potential window of ca. 4 V and hence can provide high energy-density. Gel-polymer electrolytes are generally prepared using organic solvents that are environmentally malignant. Hence, replacement of organic solvents with water in gel-polymer electrolytes is desirable which also minimizes the device cost substantially. The water containing gel-polymer electrolytes, called hydrogel-polymer electrolytes, are, however, limited by a low operating potential-window of only about 1.23 V. This article reviews salient features of electrochemical capacitors employing hydrogel-polymer electrolytes.

Properties Of Castor Oil Impregnated All-Polypropylene And Polypropylene-Paper Capacitors

In view of its non-toxicity, and good dielectric properties, castor oil, a polar liquid dielectric of vegetable origin is suggested as a possible alternative to PCB's for capacitor applications. In this paper the dielectric properties (including partial discharge behavior), of all-polypropylene and paper-polypropylene capacitors with castor oil as impregnant, are reported. The paper also contains results of life studies conducted under accelerated electrical and thermal stresses when they are occurring both individually and combined. The data obtained have been statistically analyzed and approximate life of the system calculated bylinear extrapolation.