A simplified method for determining the high frequency induction motor equivalent electrical circuit parameters to be used in EMI effect

The aim of this paper is to present a simple method for determining the high frequency parameters of a three-phase induction motor to be used in studies involving variable speed drives with PWM three-phase inverters, in which it is necessary to check the effects caused to the motor by the electromagnetic interference, (EMI) in the differential mode, as well as in the common mode. The motor parameters determination is generally performed in adequate laboratories using accurate instruments, such as very expensive RLC bridges. The method proposed here consists in the identification of the motor equivalent electrical circuit parameters in rated frequency and in high frequency through characteristic tests in the laboratory, together with the use of characteristic equations and curves, shown in the references to be mentioned for determining the motor high frequency parasite capacitances and also through system simulations using dedicated software, like Pspice, determining the characteristic waveforms involved in the differential and common mode phenomena, comparing and validating the procedure through published papers [01].

Explicit Expressions for Solar Panel Equivalent Circuit Parameters Based on Analytical Formulation and the Lambert W-Function

Due to the high dependence of photovoltaic energy efficiency on environmental conditions (temperature, irradiation...), it is quite important to perform some analysis focusing on the characteristics of photovoltaic devices in order to optimize energy production, even for small-scale users. The use of equivalent circuits is the preferred option to analyze solar cells/panels performance. However, the aforementioned small-scale users rarely have the equipment or expertise to perform large testing/calculation campaigns, the only information available for them being the manufacturer datasheet. The solution to this problem is the development of new and simple methods to define equivalent circuits able to reproduce the behavior of the panel for any working condition, from a very small amount of information. In the present work a direct and completely explicit method to extract solar cell parameters from the manufacturer datasheet is presented and tested. This method is based on analytical formulation which includes the use of the Lambert W-function to turn the series resistor equation explicit. The presented method is used to analyze commercial solar panel performance (i.e., the current-voltage–I-V–curve) at different levels of irradiation and temperature. The analysis performed is based only on the information included in the manufacturer’s datasheet.

Explicit expressions for solar panel equivalent circuit parameters based on analytical formulation and the Lambert W - Function

Due to the high dependence of photovoltaic energy efficiency on environmental conditions (temperature, irradiation...), it is quite important to perform some analysis focusing on the characteristics of photovoltaic devices in order to optimize energy production, even for small-scale users. The use of equivalent circuits is the preferred option to analyze solar cells/panels performance. However, the aforementioned small-scale users rarely have the equipment or expertise to perform large testing/calculation campaigns, the only information available for them being the manufacturer datasheet. The solution to this problem is the development of new and simple methods to define equivalent circuits able to reproduce the behavior of the panel for any working condition, from a very small amount of information. In the present work a direct and completely explicit method to extract solar cell parameters from the manufacturer datasheet is presented and tested. This method is based on analytical formulation which includes the use of the Lambert W-function to turn the series resistor equation explicit. The presented method is used to analyze the performance (i.e., the I - V curve) of a commercial solar panel at different levels of irradiation and temperature. The analysis performed is based only on the information included in the manufacturer's datasheet.

New method for analytical photovoltaic parameters identification: meeting manufacturer’s datasheet for different ambient conditions

At present, photovoltaic energy is one of the most important renewable energy sources. The demand for solar panels has been continuously growing, both in the industrial electric sector and in the private sector. In both cases the analysis of the solar panel efficiency is extremely important in order to maximize the energy production. In order to have a more efficient photovoltaic system, the most accurate understanding of this system is required. However, in most of the cases the only information available in this matter is reduced, the experimental testing of the photovoltaic device being out of consideration, normally for budget reasons. Several methods, normally based on an equivalent circuit model, have been developed to extract the I-V curve of a photovoltaic device from the small amount of data provided by the manufacturer. The aim of this paper is to present a fast, easy, and accurate analytical method, developed to calculate the equivalent circuit parameters of a solar panel from the only data that manufacturers usually provide. The calculated circuit accurately reproduces the solar panel behavior, that is, the I-V curve. This fact being extremely important for practical reasons such as selecting the best solar panel in the market for a particular purpose, or maximize the energy extraction with MPPT (Maximum Peak Power Tracking) methods.

Data analysis in multiple-frequency bioelectrical impedance analysis

The performance of three analytical methods for multiple-frequency bioelectrical impedance analysis (MFBIA) data was assessed. The methods were the established method of Cole and Cole, the newly proposed method of Siconolfi and co-workers and a modification of this procedure. Method performance was assessed from the adequacy of the curve fitting techniques, as judged by the correlation coefficient and standard error of the estimate, and the accuracy of the different methods in determining the theoretical values of impedance parameters describing a set of model electrical circuits. The experimental data were well fitted by all curve-fitting procedures (r = 0.9 with SEE 0.3 to 3.5% or better for most circuit-procedure combinations). Cole-Cole modelling provided the most accurate estimates of circuit impedance values, generally within 1-2% of the theoretical values, followed by the Siconolfi procedure using a sixth-order polynomial regression (1-6% variation). None of the methods, however, accurately estimated circuit parameters when the measured impedances were low (<20 Omega) reflecting the electronic limits of the impedance meter used. These data suggest that Cole-Cole modelling remains the preferred method for the analysis of MFBIA data.

An electromagnetic-field method modeling of a radial line planar antenna with coupling probes

This communications describes an electromagnetic model of a radial line planar antenna consisting of a radial guide with one central probe and many peripheral probes arranged in concentric circles feeding an array of antenna elements such as patches or wire curls. The model takes into account interactions between the coupling probes while assuming isolation of radiating elements. Based on this model, computer programs are developed to determine equivalent circuit parameters of the feed network and the radiation pattern of the radial line planar antenna. Comparisons are made between the present model and the two-probe model developed earlier by other researchers.

Analysis and design of sinusoidal quadrature RC-oscillators

Modern telecommunication equipment requires components that operate in many different frequency bands and support multiple communication standards, to cope with the growing demand for higher data rate. Also, a growing number of standards are adopting the use of spectrum efficient digital modulations, such as quadrature amplitude modulation (QAM) and orthogonal frequency division multiplexing (OFDM). These modulation schemes require accurate quadrature oscillators, which makes the quadrature oscillator a key block in modern radio frequency (RF) transceivers. The wide tuning range characteristics of inductorless quadrature oscillators make them natural candidates, despite their higher phase noise, in comparison with LC-oscillators. This thesis presents a detailed study of inductorless sinusoidal quadrature oscillators. Three quadrature oscillators are investigated: the active coupling RC-oscillator, the novel capacitive coupling RCoscillator, and the two-integrator oscillator. The thesis includes a detailed analysis of the Van der Pol oscillator (VDPO). This is used as a base model oscillator for the analysis of the coupled oscillators. Hence, the three oscillators are approximated by the VDPO. From the nonlinear Van der Pol equations, the oscillators’ key parameters are obtained. It is analysed first the case without component mismatches and then the case with mismatches. The research is focused on determining the impact of the components’ mismatches on the oscillator key parameters: frequency, amplitude-, and quadrature-errors. Furthermore, the minimization of the errors by adjusting the circuit parameters is addressed. A novel quadrature RC-oscillator using capacitive coupling is proposed. The advantages of using the capacitive coupling are that it is noiseless, requires a small area, and has low power dissipation. The equations of the oscillation amplitude, frequency, quadrature-error, and amplitude mismatch are derived. The theoretical results are confirmed by simulation and by measurement of two prototypes fabricated in 130 nm standard complementary metal-oxide-semiconductor (CMOS) technology. The measurements reveal that the power increase due to the coupling is marginal, leading to a figure-of-merit of -154.8 dBc/Hz. These results are consistent with the noiseless feature of this coupling and are comparable to those of the best state-of-the-art RC-oscillators, in the GHz range, but with the lowest power consumption (about 9 mW). The results for the three oscillators show that the amplitude- and the quadrature-errors are proportional to the component mismatches and inversely proportional to the coupling strength. Thus, increasing the coupling strength decreases both the amplitude- and quadrature-errors. With proper coupling strength, a quadrature error below 1° and amplitude imbalance below 1% are obtained. Furthermore, the simulations show that increasing the coupling strength reduces the phase noise. Hence, there is no trade-off between phase noise and quadrature error. In the twointegrator oscillator study, it was found that the quadrature error can be eliminated by adjusting the transconductances to compensate the capacitance mismatch. However, to obtain outputs in perfect quadrature one must allow some amplitude error.

Extracción de parámetros de un resonador FBAR por optimización

L’objectiu d’aquest projecte que consisteix a elaborar un algoritme d’optimització que permeti, mitjançant un ajust de dades per mínims quadrats, la extracció dels paràmetres del circuit equivalent que composen el model teòric d’un ressonador FBAR, a partir de les mesures dels paràmetres S. Per a dur a terme aquest treball, es desenvolupa en primer lloc tota la teoria necessària de ressonadors FBAR. Començant pel funcionament i l’estructura, i mostrant especial interès en el modelat d’aquests ressonadors mitjançant els models de Mason, Butterworth Van-Dyke i BVD Modificat. En segon terme, s’estudia la teoria sobre optimització i programació No-Lineal. Un cop s’ha exposat la teoria, es procedeix a la descripció de l’algoritme implementat. Aquest algoritme utilitza una estratègia de múltiples passos que agilitzen l'extracció dels paràmetres del ressonador.

A Multi-Objective Antenna Placement Genetic Algorithm for Matched Array Synthesis on Complex Platforms

A Multi-Objective Antenna Placement Genetic Algorithm (MO-APGA) has been proposed for the synthesis of matched antenna arrays on complex platforms. The total number of antennas required, their position on the platform, location of loads, loading circuit parameters, decoupling and matching network topology, matching network parameters and feed network parameters are optimized simultaneously. The optimization goal was to provide a given minimum gain, specific gain discrimination between the main and back lobes and broadband performance. This algorithm is developed based on the non-dominated sorting genetic algorithm (NSGA-II) and Minimum Spanning Tree (MST) technique for producing diverse solutions when the number of objectives is increased beyond two. The proposed method is validated through the design of a wideband airborne SAR

Reconhecimento de padrões de falhas em motores trifásicos utilizando redes neurais

This work presents a diagnosis faults system (rotor, stator, and contamination) of three-phase induction motor through equivalent circuit parameters and using techniques patterns recognition. The technology fault diagnostics in engines are evolving and becoming increasingly important in the field of electrical machinery. The neural networks have the ability to classify non-linear relationships between signals through the patterns identification of signals related. It is carried out induction motor´s simulations through the program Matlab R & Simulink R , and produced some faults from modifications in the equivalent circuit parameters. A system is implemented with multiples classifying neural network two neural networks to receive these results and, after well-trained, to accomplish the identification of fault´s pattern

Método experimental para determinação das capacitancias parasitas do motor de indução trifásico acionado por inversor MLP

A proposta deste trabalho é apresentar uma nova metodologia para determinação experimental das capacitancias parasitas do motor de indução trifásico de rotor em gaiola. As capacitancias parasitas fazem parte do circuito equivalente do motor para estudos de interferência eletromagnética causada no motor de indução em modo comum quando ele for acionado por inversor controlado por modulação por largura de pulsos (MLP). Os procedimentos propostos para o desenvolvimento deste novo método consistem em: a) determinação dos parâmetros do circuito equivalente do motor de indução trifásico, em regime permanente, através de ensaio em laboratório; b) estabelecer configurações de ligações entre o inversor MLP e o motor para medições das grandezas de interesse que são as seguintes: tensões de modo comum e de eixo, correntes de fuga e de eixo, através de circuito de medição desenvolvido para este fim; c) calcular os valores das capacitancias parasitas entre estator e carcaça do motor; estator e rotor; rotor e carcaça e de rolamento utilizando a expressão matemática da definição de capacitancia; d) utilizar o software Pspice para simular o sistema motor de indução trifásico, alimentado por inversor MLP, com os circuitos equivalentes em baixas e altas frequências; e) obter as formas de onda características do fenômeno de modo comum.

Inverter-fed linear asynchronous machine

The behaviors of an arc-shaped stator induction machine (the sector-motor) and a disc-secondary linear induction motor are analyzed in this work for different values of the frequency. Variable frequency is produced by a voltage source controlled-current inverter which keeps constant the r.m.s. value of the phase current, also assuring a sinusoidal waveform. For the simulations of the machine developed thrust, an equivalent circuit is used. It is obtained through the application of the one-dimensional theory to the modeling. The circuit parameters take into account the end effects, always present is these kind of machines. The phase current waveforms are analyzed for their harmonic contents. Experimental measurements were carried out in laboratory and are presented with the simulations, for comparison.

Comportamento dinâmico de suspensão eletromecânica: análise da resposta devido ao amortecimento e à rigidez não linear

Pós-graduação em Engenharia Elétrica - FEB

Diverse levels of an inwardly rectifying potassium conductance generate heterogeneous neuronal behavior in a population of dorsal cochlear nucleus pyramidal neurons

Leao RM, Li S, Doiron B, Tzounopoulos T. Diverse levels of an inwardly rectifying potassium conductance generate heterogeneous neuronal behavior in a population of dorsal cochlear nucleus pyramidal neurons. J Neurophysiol 107: 3008-3019, 2012. First published February 29, 2012; doi:10.1152/jn.00660.2011.-Homeostatic mechanisms maintain homogeneous neuronal behavior among neurons that exhibit substantial variability in the expression levels of their ionic conductances. In contrast, the mechanisms, which generate heterogeneous neuronal behavior across a neuronal population, remain poorly understood. We addressed this problem in the dorsal cochlear nucleus, where principal neurons exist in two qualitatively distinct states: spontaneously active or not spontaneously active. Our studies reveal that distinct activity states are generated by the differential levels of a Ba2+-sensitive, inwardly rectifying potassium conductance (K-ir). Variability in K-ir maximal conductance causes variations in the resting membrane potential (RMP). Low K-ir conductance depolarizes RMP to voltages above the threshold for activating subthreshold-persistent sodium channels (Na-p). Once Na-p channels are activated, the RMP becomes unstable, and spontaneous firing is triggered. Our results provide a biophysical mechanism for generating neural heterogeneity, which may play a role in the encoding of sensory information.

On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors

La temperatura es una preocupación que juega un papel protagonista en el diseño de circuitos integrados modernos. El importante aumento de las densidades de potencia que conllevan las últimas generaciones tecnológicas ha producido la aparición de gradientes térmicos y puntos calientes durante el funcionamiento normal de los chips. La temperatura tiene un impacto negativo en varios parámetros del circuito integrado como el retardo de las puertas, los gastos de disipación de calor, la fiabilidad, el consumo de energía, etc. Con el fin de luchar contra estos efectos nocivos, la técnicas de gestión dinámica de la temperatura (DTM) adaptan el comportamiento del chip en función en la información que proporciona un sistema de monitorización que mide en tiempo de ejecución la información térmica de la superficie del dado. El campo de la monitorización de la temperatura en el chip ha llamado la atención de la comunidad científica en los últimos años y es el objeto de estudio de esta tesis. Esta tesis aborda la temática de control de la temperatura en el chip desde diferentes perspectivas y niveles, ofreciendo soluciones a algunos de los temas más importantes. Los niveles físico y circuital se cubren con el diseño y la caracterización de dos nuevos sensores de temperatura especialmente diseñados para los propósitos de las técnicas DTM. El primer sensor está basado en un mecanismo que obtiene un pulso de anchura variable dependiente de la relación de las corrientes de fuga con la temperatura. De manera resumida, se carga un nodo del circuito y posteriormente se deja flotando de tal manera que se descarga a través de las corrientes de fugas de un transistor; el tiempo de descarga del nodo es la anchura del pulso. Dado que la anchura del pulso muestra una dependencia exponencial con la temperatura, la conversión a una palabra digital se realiza por medio de un contador logarítmico que realiza tanto la conversión tiempo a digital como la linealización de la salida. La estructura resultante de esta combinación de elementos se implementa en una tecnología de 0,35 _m. El sensor ocupa un área muy reducida, 10.250 nm2, y consume muy poca energía, 1.05-65.5nW a 5 muestras/s, estas cifras superaron todos los trabajos previos en el momento en que se publicó por primera vez y en el momento de la publicación de esta tesis, superan a todas las implementaciones anteriores fabricadas en el mismo nodo tecnológico. En cuanto a la precisión, el sensor ofrece una buena linealidad, incluso sin calibrar; se obtiene un error 3_ de 1,97oC, adecuado para tratar con las aplicaciones de DTM. Como se ha explicado, el sensor es completamente compatible con los procesos de fabricación CMOS, este hecho, junto con sus valores reducidos de área y consumo, lo hacen especialmente adecuado para la integración en un sistema de monitorización de DTM con un conjunto de monitores empotrados distribuidos a través del chip. Las crecientes incertidumbres de proceso asociadas a los últimos nodos tecnológicos comprometen las características de linealidad de nuestra primera propuesta de sensor. Con el objetivo de superar estos problemas, proponemos una nueva técnica para obtener la temperatura. La nueva técnica también está basada en las dependencias térmicas de las corrientes de fuga que se utilizan para descargar un nodo flotante. La novedad es que ahora la medida viene dada por el cociente de dos medidas diferentes, en una de las cuales se altera una característica del transistor de descarga |la tensión de puerta. Este cociente resulta ser muy robusto frente a variaciones de proceso y, además, la linealidad obtenida cumple ampliamente los requisitos impuestos por las políticas DTM |error 3_ de 1,17oC considerando variaciones del proceso y calibrando en dos puntos. La implementación de la parte sensora de esta nueva técnica implica varias consideraciones de diseño, tales como la generación de una referencia de tensión independiente de variaciones de proceso, que se analizan en profundidad en la tesis. Para la conversión tiempo-a-digital, se emplea la misma estructura de digitalización que en el primer sensor. Para la implementación física de la parte de digitalización, se ha construido una biblioteca de células estándar completamente nueva orientada a la reducción de área y consumo. El sensor resultante de la unión de todos los bloques se caracteriza por una energía por muestra ultra baja (48-640 pJ) y un área diminuta de 0,0016 mm2, esta cifra mejora todos los trabajos previos. Para probar esta afirmación, se realiza una comparación exhaustiva con más de 40 propuestas de sensores en la literatura científica. Subiendo el nivel de abstracción al sistema, la tercera contribución se centra en el modelado de un sistema de monitorización que consiste de un conjunto de sensores distribuidos por la superficie del chip. Todos los trabajos anteriores de la literatura tienen como objetivo maximizar la precisión del sistema con el mínimo número de monitores. Como novedad, en nuestra propuesta se introducen nuevos parámetros de calidad aparte del número de sensores, también se considera el consumo de energía, la frecuencia de muestreo, los costes de interconexión y la posibilidad de elegir diferentes tipos de monitores. El modelo se introduce en un algoritmo de recocido simulado que recibe la información térmica de un sistema, sus propiedades físicas, limitaciones de área, potencia e interconexión y una colección de tipos de monitor; el algoritmo proporciona el tipo seleccionado de monitor, el número de monitores, su posición y la velocidad de muestreo _optima. Para probar la validez del algoritmo, se presentan varios casos de estudio para el procesador Alpha 21364 considerando distintas restricciones. En comparación con otros trabajos previos en la literatura, el modelo que aquí se presenta es el más completo. Finalmente, la última contribución se dirige al nivel de red, partiendo de un conjunto de monitores de temperatura de posiciones conocidas, nos concentramos en resolver el problema de la conexión de los sensores de una forma eficiente en área y consumo. Nuestra primera propuesta en este campo es la introducción de un nuevo nivel en la jerarquía de interconexión, el nivel de trillado (o threshing en inglés), entre los monitores y los buses tradicionales de periféricos. En este nuevo nivel se aplica selectividad de datos para reducir la cantidad de información que se envía al controlador central. La idea detrás de este nuevo nivel es que en este tipo de redes la mayoría de los datos es inútil, porque desde el punto de vista del controlador sólo una pequeña cantidad de datos |normalmente sólo los valores extremos| es de interés. Para cubrir el nuevo nivel, proponemos una red de monitorización mono-conexión que se basa en un esquema de señalización en el dominio de tiempo. Este esquema reduce significativamente tanto la actividad de conmutación sobre la conexión como el consumo de energía de la red. Otra ventaja de este esquema es que los datos de los monitores llegan directamente ordenados al controlador. Si este tipo de señalización se aplica a sensores que realizan conversión tiempo-a-digital, se puede obtener compartición de recursos de digitalización tanto en tiempo como en espacio, lo que supone un importante ahorro de área y consumo. Finalmente, se presentan dos prototipos de sistemas de monitorización completos que de manera significativa superan la características de trabajos anteriores en términos de área y, especialmente, consumo de energía. Abstract Temperature is a first class design concern in modern integrated circuits. The important increase in power densities associated to recent technology evolutions has lead to the apparition of thermal gradients and hot spots during run time operation. Temperature impacts several circuit parameters such as speed, cooling budgets, reliability, power consumption, etc. In order to fight against these negative effects, dynamic thermal management (DTM) techniques adapt the behavior of the chip relying on the information of a monitoring system that provides run-time thermal information of the die surface. The field of on-chip temperature monitoring has drawn the attention of the scientific community in the recent years and is the object of study of this thesis. This thesis approaches the matter of on-chip temperature monitoring from different perspectives and levels, providing solutions to some of the most important issues. The physical and circuital levels are covered with the design and characterization of two novel temperature sensors specially tailored for DTM purposes. The first sensor is based upon a mechanism that obtains a pulse with a varying width based on the variations of the leakage currents on the temperature. In a nutshell, a circuit node is charged and subsequently left floating so that it discharges away through the subthreshold currents of a transistor; the time the node takes to discharge is the width of the pulse. Since the width of the pulse displays an exponential dependence on the temperature, the conversion into a digital word is realized by means of a logarithmic counter that performs both the timeto- digital conversion and the linearization of the output. The structure resulting from this combination of elements is implemented in a 0.35_m technology and is characterized by very reduced area, 10250 nm2, and power consumption, 1.05-65.5 nW at 5 samples/s, these figures outperformed all previous works by the time it was first published and still, by the time of the publication of this thesis, they outnumber all previous implementations in the same technology node. Concerning the accuracy, the sensor exhibits good linearity, even without calibration it displays a 3_ error of 1.97oC, appropriate to deal with DTM applications. As explained, the sensor is completely compatible with standard CMOS processes, this fact, along with its tiny area and power overhead, makes it specially suitable for the integration in a DTM monitoring system with a collection of on-chip monitors distributed across the chip. The exacerbated process fluctuations carried along with recent technology nodes jeop-ardize the linearity characteristics of the first sensor. In order to overcome these problems, a new temperature inferring technique is proposed. In this case, we also rely on the thermal dependencies of leakage currents that are used to discharge a floating node, but now, the result comes from the ratio of two different measures, in one of which we alter a characteristic of the discharging transistor |the gate voltage. This ratio proves to be very robust against process variations and displays a more than suficient linearity on the temperature |1.17oC 3_ error considering process variations and performing two-point calibration. The implementation of the sensing part based on this new technique implies several issues, such as the generation of process variations independent voltage reference, that are analyzed in depth in the thesis. In order to perform the time-to-digital conversion, we employ the same digitization structure the former sensor used. A completely new standard cell library targeting low area and power overhead is built from scratch to implement the digitization part. Putting all the pieces together, we achieve a complete sensor system that is characterized by ultra low energy per conversion of 48-640pJ and area of 0.0016mm2, this figure outperforms all previous works. To prove this statement, we perform a thorough comparison with over 40 works from the scientific literature. Moving up to the system level, the third contribution is centered on the modeling of a monitoring system consisting of set of thermal sensors distributed across the chip. All previous works from the literature target maximizing the accuracy of the system with the minimum number of monitors. In contrast, we introduce new metrics of quality apart form just the number of sensors; we consider the power consumption, the sampling frequency, the possibility to consider different types of monitors and the interconnection costs. The model is introduced in a simulated annealing algorithm that receives the thermal information of a system, its physical properties, area, power and interconnection constraints and a collection of monitor types; the algorithm yields the selected type of monitor, the number of monitors, their position and the optimum sampling rate. We test the algorithm with the Alpha 21364 processor under several constraint configurations to prove its validity. When compared to other previous works in the literature, the modeling presented here is the most complete. Finally, the last contribution targets the networking level, given an allocated set of temperature monitors, we focused on solving the problem of connecting them in an efficient way from the area and power perspectives. Our first proposal in this area is the introduction of a new interconnection hierarchy level, the threshing level, in between the monitors and the traditional peripheral buses that applies data selectivity to reduce the amount of information that is sent to the central controller. The idea behind this new level is that in this kind of networks most data are useless because from the controller viewpoint just a small amount of data |normally extreme values| is of interest. To cover the new interconnection level, we propose a single-wire monitoring network based on a time-domain signaling scheme that significantly reduces both the switching activity over the wire and the power consumption of the network. This scheme codes the information in the time domain and allows a straightforward obtention of an ordered list of values from the maximum to the minimum. If the scheme is applied to monitors that employ TDC, digitization resource sharing is achieved, producing an important saving in area and power consumption. Two prototypes of complete monitoring systems are presented, they significantly overcome previous works in terms of area and, specially, power consumption.