Design of boundary-scan testing in CMOS image sensors for industrial applications: internship repor

Tests on printed circuit boards and integrated circuits are widely used in industry,resulting in reduced design time and cost of a project. The functional and connectivity tests in this type of circuits soon began to be a concern for the manufacturers, leading to research for solutions that would allow a reliable, quick, cheap and universal solution. Initially, using test schemes were based on a set of needles that was connected to inputs and outputs of the integrated circuit board (bed-of-nails), to which signals were applied, in order to verify whether the circuit was according to the specifications and could be assembled in the production line. With the development of projects, circuit miniaturization, improvement of the production processes, improvement of the materials used, as well as the increase in the number of circuits, it was necessary to search for another solution. Thus Boundary-Scan Testing was developed which operates on the border of integrated circuits and allows testing the connectivity of the input and the output ports of a circuit. The Boundary-Scan Testing method was converted into a standard, in 1990, by the IEEE organization, being known as the IEEE 1149.1 Standard. Since then a large number of manufacturers have adopted this standard in their products. This master thesis has, as main objective: the design of Boundary-Scan Testing in an image sensor in CMOS technology, analyzing the standard requirements, the process used in the prototype production, developing the design and layout of Boundary-Scan and analyzing obtained results after production. Chapter 1 presents briefly the evolution of testing procedures used in industry, developments and applications of image sensors and the motivation for the use of architecture Boundary-Scan Testing. Chapter 2 explores the fundamentals of Boundary-Scan Testing and image sensors, starting with the Boundary-Scan architecture defined in the Standard, where functional blocks are analyzed. This understanding is necessary to implement the design on an image sensor. It also explains the architecture of image sensors currently used, focusing on sensors with a large number of inputs and outputs.Chapter 3 describes the design of the Boundary-Scan implemented and starts to analyse the design and functions of the prototype, the used software, the designs and simulations of the functional blocks of the Boundary-Scan implemented. Chapter 4 presents the layout process used based on the design developed on chapter 3, describing the software used for this purpose, the planning of the layout location (floorplan) and its dimensions, the layout of individual blocks, checks in terms of layout rules, the comparison with the final design and finally the simulation. Chapter 5 describes how the functional tests were performed to verify the design compliancy with the specifications of Standard IEEE 1149.1. These tests were focused on the application of signals to input and output ports of the produced prototype. Chapter 6 presents the conclusions that were taken throughout the execution of the work.

Controlador Boundary-Scan

A crescente complexidade dos sistemas electrónicos associada a um desenvolvimento nas tecnologias de encapsulamento levou à miniaturização dos circuitos integrados, provocando dificuldades e limitações no diagnóstico e detecção de falhas, diminuindo drasticamente a aplicabilidade dos equipamentos ICT. Como forma de lidar com este problema surgiu a infra-estrutura Boundary Scan descrita na norma IEEE1149.1 “Test Access Port and Boundary-Scan Architecture”, aprovada em 1990. Sendo esta solução tecnicamente viável e interessante economicamente para o diagnóstico de defeitos, efectua também outras aplicações. O SVF surgiu do desejo de incutir e fazer com que os fornecedores independentes incluíssem a norma IEEE 1149.1, é desenvolvido num formato ASCII, com o objectivo de enviar sinais, aguardar pela sua resposta, segundo a máscara de dados baseada na norma IEEE1149.1. Actualmente a incorporação do Boundary Scan nos circuitos integrados está em grande expansão e consequentemente usufrui de uma forte implementação no mercado. Neste contexto o objectivo da dissertação é o desenvolvimento de um controlador boundary scan que implemente uma interface com o PC e possibilite o controlo e monitorização da aplicação de teste ao PCB. A arquitectura do controlador desenvolvido contém um módulo de Memória de entrada, um Controlador TAP e uma Memória de saída. A implementação do controlador foi feita através da utilização de uma FPGA, é um dispositivo lógico reconfiguráveis constituído por blocos lógicos e por uma rede de interligações, ambos configuráveis, que permitem ao utilizador implementar as mais variadas funções digitais. A utilização de uma FPGA tem a vantagem de permitir a versatilidade do controlador, facilidade na alteração do seu código e possibilidade de inserir mais controladores dentro da FPGA. Foi desenvolvido o protocolo de comunicação e sincronização entre os vários módulos, permitindo o controlo e monitorização dos estímulos enviados e recebidos ao PCB, executados automaticamente através do software do Controlador TAP e de acordo com a norma IEEE 1149.1. A solução proposta foi validada por simulação utilizando o simulador da Xilinx. Foram analisados todos os sinais que constituem o controlador e verificado o correcto funcionamento de todos os seus módulos. Esta solução executa todas as sequências pretendidas e necessárias (envio de estímulos) à realização dos testes ao PCB. Recebe e armazena os dados obtidos, enviando-os posteriormente para a memória de saída. A execução do trabalho permitiu concluir que os projectos de componentes electrónicos tenderão a ser descritos num nível de abstracção mais elevado, recorrendo cada vez mais ao uso de linguagens de hardware, no qual o VHDL é uma excelente ferramenta de programação. O controlador desenvolvido será uma ferramenta bastante útil e versátil para o teste de PCBs e outras funcionalidades disponibilizadas pelas infra-estruturas BS.

Desenvolvimento de um Controlador de Boundary Scan (Ieee 1149.1)

Mestrado em Engenharia Electrotécnica e de Computadores - Área de Especialização em Automação e Sistemas

Testing of Interposer-Based 2.5D Integrated Circuits

The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.

Inserção de testabilidade em um núcleo pré-projetado de um microcontrolador 8051 fonte compatível

No intuito de validar seus projetos de sistemas integrados, o Grupo de Microeletrônica da UFRGS tem investido na inserção de estruturas de teste nos núcleos de hardware que tem desenvolvido. Um exemplo de tal tipo de sistema é a “caneta tradutora”, especificada e parcialmente desenvolvida por Denis Franco. Esta caneta se utiliza de um microcontrolador 8051 descrito em VHDL, o qual ainda carece de estruturas dedicadas com funções orientadas à testabilidade. Este trabalho exemplifica a integração de teste em um circuito eletrônico préprojetado. Neste caso específico, foi utilizado o microcontrolador 8051 fonte compatível que será inserido no contexto da caneta tradutora. O método utilizado apoiou-se na norma IEEE1149.1, destinada a definir uma infra-estrutura baseada na técnica do boundary scan para o teste de placas de circuito impresso. São apresentadas características de testabilidade desenvolvidas para o microcontrolador, utilizando-se a técnica do boundary scan em sua periferia e a técnica do scan path em seu núcleo. A inserção destas características de teste facilita a depuração e testes em nível de sistema, imaginando-se o sistema como algo maior, fazendo parte do sistema da caneta tradutora como um todo. São elaborados exemplos de testes, demonstrando a funcionalidade do circuito de teste inserido neste núcleo e a possibilidade de detecção de falhas em pontos distintos do sistema. Finalmente, avalia-se o custo associado à integração desta infra-estrutura de teste, tanto em termos de acréscimo de área em silício, quanto em termos de degradação de desempenho do sistema.

Analysis of crystallographic slip and grain boundary sliding in a Ti-45Al-2Nb-2Mn (at%)-0.8 vol%TiB2 alloy by high temperature in situ mechanical testing

This work aims to contribute to a further understanding of the fundamentals of crystallographic slip and grain boundary sliding in the γ-TiAl Ti–45Al–2Nb–2Mn (at%)–0.8 vol%TiB2 intermetallic alloy, by means of in situ high-temperature tensile testing combined with electron backscatter diffraction (EBSD). Several microstructures, containing different fractions and sizes of lamellar colonies and equiaxed γ-grains, were fabricated by either centrifugal casting or powder metallurgy, followed by heat treatment at 1300 °C and furnace cooling. in situ tensile and tensile-creep experiments were performed in a scanning electron microscope (SEM) at temperatures ranging from 580 °C to 700 °C. EBSD was carried out in selected regions before and after straining. Our results suggest that, during constant strain rate tests, true twin γ/γ interfaces are the weakest barriers to dislocations and, thus, that the relevant length scale might be influenced by the distance between non-true twin boundaries. Under creep conditions both grain/colony boundary sliding (G/CBS) and crystallographic slip are observed to contribute to deformation. The incidence of boundary sliding is particularly high in γ grains of duplex microstructures. The slip activity during creep deformation in different microstructures was evaluated by trace analysis. Special emphasis was placed in distinguishing the compliance of different slip events with the Schmid law with respect to the applied stress.

Post-processing and visualization techniques in 2D boundary element analysis

Most post-processors for boundary element (BE) analysis use an auxiliary domain mesh to display domain results, working against the profitable modelling process of a pure boundary discretization. This paper introduces a novel visualization technique which preserves the basic properties of the boundary element methods. The proposed algorithm does not require any domain discretization and is based on the direct and automatic identification of isolines. Another critical aspect of the visualization of domain results in BE analysis is the effort required to evaluate results in interior points. In order to tackle this issue, the present article also provides a comparison between the performance of two different BE formulations (conventional and hybrid). In addition, this paper presents an overview of the most common post-processing and visualization techniques in BE analysis, such as the classical algorithms of scan line and the interpolation over a domain discretization. The results presented herein show that the proposed algorithm offers a very high performance compared with other visualization procedures.

Investigation on the intergranular corrosion resistance of the AISI 316L(N) stainless steel after long time creep testing at 600 degrees C

The effect of precipitation on the corrosion resistance of AISI 316L(N) stainless steel previously exposed to creep tests at 600 degrees C for periods of up to 10 years, has been studied. The corrosion resistance was investigated in 2 M H(2)SO(4)+0.5 M NaCl+0.01 M KSCN solution at 30 degrees C by electrochemical methods. The results showed that the susceptibility to intergranular corrosion was highly affected by aging at 600 degrees C and creep testing time. The intergranular corrosion resistance decreased by more than twenty times when the creep testing time increased from 7500 h to 85,000 h. The tendency to passivation decreased and less protective films were formed on the creep tested samples. All tested samples also showed susceptibility to pitting. Grain boundary M(23)C(6) carbides were not found after long-term exposure at 600 degrees C and the corrosion behavior of the creep tested samples was attributed to intermetallic phases (mainly sigma phase) precipitation. (C) 2007 Elsevier Inc. All rights reserved.

A framework for table driven testing of Java classes

With the advent of object-oriented languages and the portability of Java, the development and use of class libraries has become widespread. Effective class reuse depends on class reliability which in turn depends on thorough testing. This paper describes a class testing approach based on modeling each test case with a tuple and then generating large numbers of tuples to thoroughly cover an input space with many interesting combinations of values. The testing approach is supported by the Roast framework for the testing of Java classes. Roast provides automated tuple generation based on boundary values, unit operations that support driver standardization, and test case templates used for code generation. Roast produces thorough, compact test drivers with low development and maintenance cost. The framework and tool support are illustrated on a number of non-trivial classes, including a graphical user interface policy manager. Quantitative results are presented to substantiate the practicality and effectiveness of the approach. Copyright (C) 2002 John Wiley Sons, Ltd.

Skin-friction measurements in high-enthalpy hypersonic boundary layers

Skin-friction measurements are reported for high-enthalpy and high-Mach-number laminar, transitional and turbulent boundary layers. The measurements were performed in a free-piston shock tunnel with air-flow Mach number, stagnation enthalpy and Reynolds numbers in the ranges of 4.4-6.7, 3-13 MJ kg(-1) and 0.16 x 10(6)-21 x 10(6), respectively. Wall temperatures were near 300 K and this resulted in ratios of wall enthalpy to flow-stagnation enthalpy in the range of 0.1-0.02. The experiments were performed using rectangular ducts. The measurements were accomplished using a new skin-friction gauge that was developed for impulse facility testing. The gauge was an acceleration compensated piezoelectric transducer and had a lowest natural frequency near 40 kHz. Turbulent skin-friction levels were measured to within a typical uncertainty of +/-7%. The systematic uncertainty in measured skin-friction coefficient was high for the tested laminar conditions; however, to within experimental uncertainty, the skin-friction and heat-transfer measurements were in agreement with the laminar theory of van Driest (1952). For predicting turbulent skin-friction coefficient, it was established that, for the range of Mach numbers and Reynolds numbers of the experiments, with cold walls and boundary layers approaching the turbulent equilibrium state, the Spalding & Chi (1964) method was the most suitable of the theories tested. It was also established that if the heat transfer rate to the wall is to be predicted, then the Spalding & Chi (1964) method should be used in conjunction with a Reynolds analogy factor near unity. If more accurate results are required, then an experimentally observed relationship between the Reynolds analogy factor and the skin-friction coefficient may be applied.

Effects of MRI scan acceleration on brain volume measurement consistency.

PURPOSE: To evaluate the effects of recent advances in magnetic resonance imaging (MRI) radiofrequency (RF) coil and parallel imaging technology on brain volume measurement consistency. MATERIALS AND METHODS: In all, 103 whole-brain MRI volumes were acquired at a clinical 3T MRI, equipped with a 12- and 32-channel head coil, using the T1-weighted protocol as employed in the Alzheimer's Disease Neuroimaging Initiative study with parallel imaging accelerations ranging from 1 to 5. An experienced reader performed qualitative ratings of the images. For quantitative analysis, differences in composite width (CW, a measure of image similarity) and boundary shift integral (BSI, a measure of whole-brain atrophy) were calculated. RESULTS: Intra- and intersession comparisons of CW and BSI measures from scans with equal acceleration demonstrated excellent scan-rescan accuracy, even at the highest acceleration applied. Pairs-of-scans acquired with different accelerations exhibited poor scan-rescan consistency only when differences in the acceleration factor were maximized. A change in the coil hardware between compared scans was found to bias the BSI measure. CONCLUSION: The most important findings are that the accelerated acquisitions appear to be compatible with the assessment of high-quality quantitative information and that for highest scan-rescan accuracy in serial scans the acquisition protocol should be kept as consistent as possible over time. J. Magn. Reson. Imaging 2012;36:1234-1240. ©2012 Wiley Periodicals, Inc.

Methods for testing association between uncertain genotypes and quantitative traits.

Interpretability and power of genome-wide association studies can be increased by imputing unobserved genotypes, using a reference panel of individuals genotyped at higher marker density. For many markers, genotypes cannot be imputed with complete certainty, and the uncertainty needs to be taken into account when testing for association with a given phenotype. In this paper, we compare currently available methods for testing association between uncertain genotypes and quantitative traits. We show that some previously described methods offer poor control of the false-positive rate (FPR), and that satisfactory performance of these methods is obtained only by using ad hoc filtering rules or by using a harsh transformation of the trait under study. We propose new methods that are based on exact maximum likelihood estimation and use a mixture model to accommodate nonnormal trait distributions when necessary. The new methods adequately control the FPR and also have equal or better power compared to all previously described methods. We provide a fast software implementation of all the methods studied here; our new method requires computation time of less than one computer-day for a typical genome-wide scan, with 2.5 M single nucleotide polymorphisms and 5000 individuals.

Side scan sonar image and geologic interpretation of the Ria de Pontevedra seafloor (Galicia, NW Spain).

High-resolution side scan sonar has been used for mapping the seafloor of the Ría de Pontevedra. Four backscatter patterns have been mapped within the Ría: (1) Pattern with isolated reflections, correlated with granite and metamorphic outcrops and located close to the coastal prominence and Ons and Onza Islands. (2) Pattern of strong reflectivity usually located around the basement outcrops and near the coastline and produced by coarse-grained sediment. (3) Pattern of weak backscatter is correlated with fine sand to mud and comprising large areas in the central and deep part of the Ría, where the bottom currents are weak. It is generally featureless, except where pockmarks and anthropogenic features are present. (4) Patches of strong and weak backscatter are located in the boundary between coarse and fine-grained sediments and they are due to the effect of strong bottom currents. The presence of megaripples associated to both patterns of strong reflectivity and sedimentary patches indicate bedload transport of sediment during high energy conditions (storms). Side scan sonar records and supplementary bathymetry, bottom samples and hydrodynamic data reveal that the distribution of seafloor sediment is strongly related to oceanographic processes and the particular morphology and topography of the Ría.

Evaluation of the MIT-Scan-T2 for Non-Destructive PCC Pavement Thickness Determination Final Report, July 2008

The MIT-Scan-T2 device is marketed as a non-destructive way to determine pavement thickness on both HMA and PCC pavements. PCC pavement thickness determination is an important incentivedisincentive measurement for the Iowa DOT and contractors. The thickness incentive can be as much as 3% of the concrete contact unit price and the disincentive can be as severe as remove and replace. This study evaluated the potential of the MIT device for PCC pavement thickness quality assurance. The limited testing indicates the unit is sufficiently repeatable and accurate enough to replace core drilling as the thickness measurement method. Further study is needed to statistically establish the single user and multi-user/device precision as well as establish an appropriate sampling protocol and PWL specification.