936 resultados para Boundary Scan


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A crescente complexidade dos sistemas electrónicos associada a um desenvolvimento nas tecnologias de encapsulamento levou à miniaturização dos circuitos integrados, provocando dificuldades e limitações no diagnóstico e detecção de falhas, diminuindo drasticamente a aplicabilidade dos equipamentos ICT. Como forma de lidar com este problema surgiu a infra-estrutura Boundary Scan descrita na norma IEEE1149.1 “Test Access Port and Boundary-Scan Architecture”, aprovada em 1990. Sendo esta solução tecnicamente viável e interessante economicamente para o diagnóstico de defeitos, efectua também outras aplicações. O SVF surgiu do desejo de incutir e fazer com que os fornecedores independentes incluíssem a norma IEEE 1149.1, é desenvolvido num formato ASCII, com o objectivo de enviar sinais, aguardar pela sua resposta, segundo a máscara de dados baseada na norma IEEE1149.1. Actualmente a incorporação do Boundary Scan nos circuitos integrados está em grande expansão e consequentemente usufrui de uma forte implementação no mercado. Neste contexto o objectivo da dissertação é o desenvolvimento de um controlador boundary scan que implemente uma interface com o PC e possibilite o controlo e monitorização da aplicação de teste ao PCB. A arquitectura do controlador desenvolvido contém um módulo de Memória de entrada, um Controlador TAP e uma Memória de saída. A implementação do controlador foi feita através da utilização de uma FPGA, é um dispositivo lógico reconfiguráveis constituído por blocos lógicos e por uma rede de interligações, ambos configuráveis, que permitem ao utilizador implementar as mais variadas funções digitais. A utilização de uma FPGA tem a vantagem de permitir a versatilidade do controlador, facilidade na alteração do seu código e possibilidade de inserir mais controladores dentro da FPGA. Foi desenvolvido o protocolo de comunicação e sincronização entre os vários módulos, permitindo o controlo e monitorização dos estímulos enviados e recebidos ao PCB, executados automaticamente através do software do Controlador TAP e de acordo com a norma IEEE 1149.1. A solução proposta foi validada por simulação utilizando o simulador da Xilinx. Foram analisados todos os sinais que constituem o controlador e verificado o correcto funcionamento de todos os seus módulos. Esta solução executa todas as sequências pretendidas e necessárias (envio de estímulos) à realização dos testes ao PCB. Recebe e armazena os dados obtidos, enviando-os posteriormente para a memória de saída. A execução do trabalho permitiu concluir que os projectos de componentes electrónicos tenderão a ser descritos num nível de abstracção mais elevado, recorrendo cada vez mais ao uso de linguagens de hardware, no qual o VHDL é uma excelente ferramenta de programação. O controlador desenvolvido será uma ferramenta bastante útil e versátil para o teste de PCBs e outras funcionalidades disponibilizadas pelas infra-estruturas BS.

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Mestrado em Engenharia Electrotécnica e de Computadores - Área de Especialização em Automação e Sistemas

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Tests on printed circuit boards and integrated circuits are widely used in industry,resulting in reduced design time and cost of a project. The functional and connectivity tests in this type of circuits soon began to be a concern for the manufacturers, leading to research for solutions that would allow a reliable, quick, cheap and universal solution. Initially, using test schemes were based on a set of needles that was connected to inputs and outputs of the integrated circuit board (bed-of-nails), to which signals were applied, in order to verify whether the circuit was according to the specifications and could be assembled in the production line. With the development of projects, circuit miniaturization, improvement of the production processes, improvement of the materials used, as well as the increase in the number of circuits, it was necessary to search for another solution. Thus Boundary-Scan Testing was developed which operates on the border of integrated circuits and allows testing the connectivity of the input and the output ports of a circuit. The Boundary-Scan Testing method was converted into a standard, in 1990, by the IEEE organization, being known as the IEEE 1149.1 Standard. Since then a large number of manufacturers have adopted this standard in their products. This master thesis has, as main objective: the design of Boundary-Scan Testing in an image sensor in CMOS technology, analyzing the standard requirements, the process used in the prototype production, developing the design and layout of Boundary-Scan and analyzing obtained results after production. Chapter 1 presents briefly the evolution of testing procedures used in industry, developments and applications of image sensors and the motivation for the use of architecture Boundary-Scan Testing. Chapter 2 explores the fundamentals of Boundary-Scan Testing and image sensors, starting with the Boundary-Scan architecture defined in the Standard, where functional blocks are analyzed. This understanding is necessary to implement the design on an image sensor. It also explains the architecture of image sensors currently used, focusing on sensors with a large number of inputs and outputs.Chapter 3 describes the design of the Boundary-Scan implemented and starts to analyse the design and functions of the prototype, the used software, the designs and simulations of the functional blocks of the Boundary-Scan implemented. Chapter 4 presents the layout process used based on the design developed on chapter 3, describing the software used for this purpose, the planning of the layout location (floorplan) and its dimensions, the layout of individual blocks, checks in terms of layout rules, the comparison with the final design and finally the simulation. Chapter 5 describes how the functional tests were performed to verify the design compliancy with the specifications of Standard IEEE 1149.1. These tests were focused on the application of signals to input and output ports of the produced prototype. Chapter 6 presents the conclusions that were taken throughout the execution of the work.

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No intuito de validar seus projetos de sistemas integrados, o Grupo de Microeletrônica da UFRGS tem investido na inserção de estruturas de teste nos núcleos de hardware que tem desenvolvido. Um exemplo de tal tipo de sistema é a “caneta tradutora”, especificada e parcialmente desenvolvida por Denis Franco. Esta caneta se utiliza de um microcontrolador 8051 descrito em VHDL, o qual ainda carece de estruturas dedicadas com funções orientadas à testabilidade. Este trabalho exemplifica a integração de teste em um circuito eletrônico préprojetado. Neste caso específico, foi utilizado o microcontrolador 8051 fonte compatível que será inserido no contexto da caneta tradutora. O método utilizado apoiou-se na norma IEEE1149.1, destinada a definir uma infra-estrutura baseada na técnica do boundary scan para o teste de placas de circuito impresso. São apresentadas características de testabilidade desenvolvidas para o microcontrolador, utilizando-se a técnica do boundary scan em sua periferia e a técnica do scan path em seu núcleo. A inserção destas características de teste facilita a depuração e testes em nível de sistema, imaginando-se o sistema como algo maior, fazendo parte do sistema da caneta tradutora como um todo. São elaborados exemplos de testes, demonstrando a funcionalidade do circuito de teste inserido neste núcleo e a possibilidade de detecção de falhas em pontos distintos do sistema. Finalmente, avalia-se o custo associado à integração desta infra-estrutura de teste, tanto em termos de acréscimo de área em silício, quanto em termos de degradação de desempenho do sistema.

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The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.

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Most post-processors for boundary element (BE) analysis use an auxiliary domain mesh to display domain results, working against the profitable modelling process of a pure boundary discretization. This paper introduces a novel visualization technique which preserves the basic properties of the boundary element methods. The proposed algorithm does not require any domain discretization and is based on the direct and automatic identification of isolines. Another critical aspect of the visualization of domain results in BE analysis is the effort required to evaluate results in interior points. In order to tackle this issue, the present article also provides a comparison between the performance of two different BE formulations (conventional and hybrid). In addition, this paper presents an overview of the most common post-processing and visualization techniques in BE analysis, such as the classical algorithms of scan line and the interpolation over a domain discretization. The results presented herein show that the proposed algorithm offers a very high performance compared with other visualization procedures.

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PURPOSE: To evaluate the effects of recent advances in magnetic resonance imaging (MRI) radiofrequency (RF) coil and parallel imaging technology on brain volume measurement consistency. MATERIALS AND METHODS: In all, 103 whole-brain MRI volumes were acquired at a clinical 3T MRI, equipped with a 12- and 32-channel head coil, using the T1-weighted protocol as employed in the Alzheimer's Disease Neuroimaging Initiative study with parallel imaging accelerations ranging from 1 to 5. An experienced reader performed qualitative ratings of the images. For quantitative analysis, differences in composite width (CW, a measure of image similarity) and boundary shift integral (BSI, a measure of whole-brain atrophy) were calculated. RESULTS: Intra- and intersession comparisons of CW and BSI measures from scans with equal acceleration demonstrated excellent scan-rescan accuracy, even at the highest acceleration applied. Pairs-of-scans acquired with different accelerations exhibited poor scan-rescan consistency only when differences in the acceleration factor were maximized. A change in the coil hardware between compared scans was found to bias the BSI measure. CONCLUSION: The most important findings are that the accelerated acquisitions appear to be compatible with the assessment of high-quality quantitative information and that for highest scan-rescan accuracy in serial scans the acquisition protocol should be kept as consistent as possible over time. J. Magn. Reson. Imaging 2012;36:1234-1240. ©2012 Wiley Periodicals, Inc.

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High-resolution side scan sonar has been used for mapping the seafloor of the Ría de Pontevedra. Four backscatter patterns have been mapped within the Ría: (1) Pattern with isolated reflections, correlated with granite and metamorphic outcrops and located close to the coastal prominence and Ons and Onza Islands. (2) Pattern of strong reflectivity usually located around the basement outcrops and near the coastline and produced by coarse-grained sediment. (3) Pattern of weak backscatter is correlated with fine sand to mud and comprising large areas in the central and deep part of the Ría, where the bottom currents are weak. It is generally featureless, except where pockmarks and anthropogenic features are present. (4) Patches of strong and weak backscatter are located in the boundary between coarse and fine-grained sediments and they are due to the effect of strong bottom currents. The presence of megaripples associated to both patterns of strong reflectivity and sedimentary patches indicate bedload transport of sediment during high energy conditions (storms). Side scan sonar records and supplementary bathymetry, bottom samples and hydrodynamic data reveal that the distribution of seafloor sediment is strongly related to oceanographic processes and the particular morphology and topography of the Ría.

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Blood flow in human aorta is an unsteady and complex phenomenon. The complex patterns are related to the geometrical features like curvature, bends, and branching and pulsatile nature of flow from left ventricle of heart. The aim of this work was to understand the effect of aorta geometry on the flow dynamics. To achieve this, 3D realistic and idealized models of descending aorta were reconstructed from Computed Tomography (CT) images of a female patient. The geometries were reconstructed using medical image processing code. The blood flow in aorta was assumed to be laminar and incompressible and the blood was assumed to be Newtonian fluid. A time dependent pulsatile and parabolic boundary condition was deployed at inlet. Steady and unsteady blood flow simulations were performed in real and idealized geometries of descending aorta using a Finite Volume Method (FVM) code. Analysis of Wall Shear Stress (WSS) distribution, pressure distribution, and axial velocity profiles were carried out in both geometries at steady and unsteady state conditions. The results obtained in thesis work reveal that the idealization of geometry underestimates the values of WSS especially near the region with sudden change of diameter. However, the resultant pressure and velocity in idealized geometry are close to those in real geometry

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It has long been known that the urban surface energy balance is different to that of a rural surface, and that heating of the urban surface after sunset gives rise to the Urban Heat Island (UHI). Less well known is how flow and turbulence structure above the urban surface are changed during different phases of the urban boundary layer (UBL). This paper presents new observations above both an urban and rural surface and investigates how much UBL structure deviates from classical behaviour. A 5-day, low wind, cloudless, high pressure period over London, UK, was chosen for analysis, during which there was a strong UHI. Boundary layer evolution for both sites was determined by the diurnal cycle in sensible heat flux, with an extended decay period of approximately 4 h for the convective UBL. This is referred to as the “Urban Convective Island” as the surrounding rural area was already stable at this time. Mixing height magnitude depended on the combination of regional temperature profiles and surface temperature. Given the daytime UHI intensity of 1.5∘C, combined with multiple inversions in the temperature profile, urban and rural mixing heights underwent opposite trends over the period, resulting in a factor of three height difference by the fifth day. Nocturnal jets undergoing inertial oscillations were observed aloft in the urban wind profile as soon as the rural boundary layer became stable: clear jet maxima over the urban surface only emerged once the UBL had become stable. This was due to mixing during the Urban Convective Island reducing shear. Analysis of turbulent moments (variance, skewness and kurtosis) showed “upside-down” boundary layer characteristics on some mornings during initial rapid growth of the convective UBL. During the “Urban Convective Island” phase, turbulence structure still resembled a classical convective boundary layer but with some influence from shear aloft, depending on jet strength. These results demonstrate that appropriate choice of Doppler lidar scan patterns can give detailed profiles of UBL flow. Insights drawn from the observations have implications for accuracy of boundary conditions when simulating urban flow and dispersion, as the UBL is clearly the result of processes driven not only by local surface conditions but also regional atmospheric structure.

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Magnetic properties of nanocrystalline NiFe(2)O(4) spinel mechanically processed for 350 h have been studied using temperature dependent from both zero-field and in-field (57)Fe Mossbauer spectrometry and magnetization measurements. The hyperfine structure allows us to distinguish two main magnetic contributions: one attributed to the crystalline grain core, which has magnetic properties similar to the NiFe(2)O(4) spinel-like structure (n-NiFe(2)O(4)) and the other one due to the disordered grain boundary region, which presents topological and chemical disorder features(d-NiFe(2)O(4)). Mossbauer spectrometry determines a large fraction for the d-NiFe(2)O(4) region(62% of total area) and also suggests a speromagnet-like structure for it. Under applied magnetic field, the n-NiFe(2)O(4) spins are canted with angle dependent on the applied field magnitude. Mossbauer data also show that even under 120 kOe no magnetic saturation is observed for the two magnetic phases. In addition, the hysteresis loops, recorded for scan field of 50 kOe, are shifted in both field and magnetization axes, for temperatures below about 50 K. The hysteresis loop shifts may be due to two main contributions: the exchange bias field at the d-NiFe(2)O(4)/n-NiFe(2)O(4) interfaces and the minor loop effect caused by a high magnetic anisotropy of the d-NiFe(2)O(4) phase. It has also been shown that the spin configuration of the spin-glass like phase is modified by the consecutive field cycles, consequently the n-NiFe(2)O(4)/d-NiFe(2)O(4) magnetic interaction is also affected in this process. (C) 2010 Elsevier B.V. All rights reserved.

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The fluid flow over bodies with complex geometry has been the subject of research of many scientists and widely explored experimentally and numerically. The present study proposes an Eulerian Immersed Boundary Method for flows simulations over stationary or moving rigid bodies. The proposed method allows the use of Cartesians Meshes. Here, two-dimensional simulations of fluid flow over stationary and oscillating circular cylinders were used for verification and validation. Four different cases were explored: the flow over a stationary cylinder, the flow over a cylinder oscillating in the flow direction, the flow over a cylinder oscillating in the normal flow direction, and a cylinder with angular oscillation. The time integration was carried out by a classical 4th order Runge-Kutta scheme, with a time step of the same order of distance between two consecutive points in x direction. High-order compact finite difference schemes were used to calculate spatial derivatives. The drag and lift coefficients, the lock-in phenomenon and vorticity contour plots were used for the verification and validation of the proposed method. The extension of the current method allowing the study of a body with different geometry and three-dimensional simulations is straightforward. The results obtained show a good agreement with both numerical and experimental results, encouraging the use of the proposed method.

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Background : In tropical countries, losses caused by bovine tick Rhipicephalus (Boophilus) microplus infestation have a tremendous economic impact on cattle production systems. Genetic variation between Bos taurus and Bos indicus to tick resistance and molecular biology tools might allow for the identification of molecular markers linked to resistance traits that could be used as an auxiliary tool in selection programs. The objective of this work was to identify QTL associated with tick resistance/susceptibility in a bovine F2 population derived from the Gyr (Bos indicus) x Holstein (Bos taurus) cross. Results: Through a whole genome scan with microsatellite markers, we were able to map six genomic regions associated with bovine tick resistance. For most QTL, we have found that depending on the tick evaluation season (dry and rainy) different sets of genes could be involved in the resistance mechanism. We identified dry season specific QTL on BTA 2 and 10, rainy season specific QTL on BTA 5, 11 and 27. We also found a highly significant genome wide QTL for both dry and rainy seasons in the central region of BTA 23. Conclusions: The experimental F2 population derived from Gyr x Holstein cross successfully allowed the identification of six highly significant QTL associated with tick resistance in cattle. QTL located on BTA 23 might be related with the bovine histocompatibility complex. Further investigation of these QTL will help to isolate candidate genes involved with tick resistance in cattle.

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We show that the one-loop effective action at finite temperature for a scalar field with quartic interaction has the same renormalized expression as at zero temperature if written in terms of a certain classical field phi(c), and if we trade free propagators at zero temperature for their finite-temperature counterparts. The result follows if we write the partition function as an integral over field eigenstates (boundary fields) of the density matrix element in the functional Schrodinger field representation, and perform a semiclassical expansion in two steps: first, we integrate around the saddle point for fixed boundary fields, which is the classical field phi(c), a functional of the boundary fields; then, we perform a saddle-point integration over the boundary fields, whose correlations characterize the thermal properties of the system. This procedure provides a dimensionally reduced effective theory for the thermal system. We calculate the two-point correlation as an example.

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Thermodiffusion in a lyotropic mixture of water and potassium laurate is investigated by means of an optical technique (Z scan) distinguishing the index variations due to the temperature gradient and the mass gradients. A phenomenological framework allowing for coupled diffusion is developed in order to analyze thermodiffusion in multicomponent systems. An observable parameter relating to the mass gradients is found to exhibit a sharp change around the critical micellar concentration, and thus may be used to detect it. The change in the slope is due to the markedly different values of the Soret coefficients of the surfactant and the micelles. The difference in the Soret coefficients is due to the fact that the micellization process reduces the energy of interaction of the ball of amphiphilic molecules with the solvent.