958 resultados para ADA compliant


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Annaul report for Iowa Workforce Development in PDF adn ADA Compliant Text File

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Compliant mechanisms can achieve a specified motion as a mechanism without relying on the use of joints and pins. They have broad application in precision mechanical devices and Micro-Electro Mechanical Systems (MEMS) but may lose accuracy and produce undesirable displacements when subjected to temperature changes. These undesirable effects can be reduced by using sensors in combination with control techniques and/or by applying special design techniques to reduce such undesirable effects at the design stage, a process generally termed ""design for precision"". This paper describes a design for precision method based on a topology optimization method (TOM) for compliant mechanisms that includes thermal compensation features. The optimization problem emphasizes actuator accuracy and it is formulated to yield optimal compliant mechanism configurations that maximize the desired output displacement when a force is applied, while minimizing undesirable thermal effects. To demonstrate the effectiveness of the method, two-dimensional compliant mechanisms are designed considering thermal compensation, and their performance is compared with compliant mechanisms designs that do not consider thermal compensation. (C) 2010 Elsevier B.V. All rights reserved.

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Adenosine deaminase (ADA) deficiency is a disorder of the purine metabolism leading to combined immunodeficiency and systemic alterations, including skeletal abnormalities. We report that ADA deficiency in mice causes a specific bone phenotype characterized by alterations of structural properties and impaired mechanical competence. These alterations are the combined result of an imbalanced receptor activator of nuclear factor-kappa B ligand (RANKL)/osteoprotegerin axis, causing decreased osteoclastogenesis and an intrinsic defect of osteoblast function with subsequent low bone formation. In vitro, osteoblasts lacking ADA displayed an altered transcriptional profile and growth reduction. Furthermore, the bone marrow microenvironment of ADA-deficient mice showed a reduced capacity to support in vitro and in vivo hematopoiesis. Treatment of ADA-deficient neonatal mice with enzyme replacement therapy, bone marrow transplantation, or gene therapy resulted in full recovery of the altered bone parameters. Remarkably, untreated ADA-severe combined immunodeficiency patients showed a similar imbalance in RANKL/osteoprotegerin levels alongside severe growth retardation. Gene therapy with ADA-transduced hematopoietic stem cells increased serum RANKL levels and children`s growth. Our results indicate that the ADA metabolism represents a crucial modulatory factor of bone cell activities and remodeling. The trials were registered at www.clinicaltrials.gov as #NCT00598481 and #NCT00599781. (Blood. 2009; 114: 3216-3226)

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An experiment was performed to characterise the movement kinematics and the electromyogram (EMG) during rhythmic voluntary flexion and extension of the wrist against different compliant (elastic-viscous-inertial) loads. Three levels of each type of load, and an unloaded condition, were employed. The movements were paced at a frequency of I Hz by an auditory metronome, and visual feedback of wrist displacement in relation to a target amplitude of 100degrees was provided. Electro-myographic recordings were obtained from flexor carpi radialis (FCR) and extensor carpi radialis brevis (ECR). The movement profiles generated in the ten experimental conditions were indistinguishable, indicating that the CNS was able to compensate completely for the imposed changes in the task dynamics. When the level of viscous load was elevated, this compensation took the form of an increase in the rate of initial rise of the flexor and the extensor EMG burst. In response to increases in inertial load, the flexor and extensor EMG bursts commenced and terminated earlier in the movement cycle, and tended to be of greater duration. When the movements were performed in opposition to an elastic load, both the onset and offset of EMG activity occurred later than in the unloaded condition. There was also a net reduction in extensor burst duration with increases in elastic load, and an increase in the rate of initial rise of the extensor burst. Less pronounced alterations in the rate of initial rise of the flexor EMG burst were also observed. In all instances, increases in the magnitude of the external load led to elevations in the overall level of muscle activation. These data reveal that the elements of the central command that are modified in response to the imposition of a compliant load are contingent, not only upon the magnitude, but also upon the character of the load.

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In this paper we present a framework for managing QoS-aware applications in a dynamic, ad-hoc, distributed environment. This framework considers an available set of wireless/mobile and fixed nodes, which may temporally form groups in order to process a set of related services, and where there is the need to support different levels of service and different combinations of quality requirements. This framework is being developed both for testing and validating an approach, based on multidimensional QoS properties, which provides service negotiation and proposal evaluation algorithms, and for assessing the suitability of the Ada language to be used in the context of dynamic, QoS-aware systems.

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Ada is really an unfortunate Lady. After years fighting against C/C++ villains, her major lift-up (Ada 95) had brought up a promise of fortune. However, a new strong villain (Java) has appeared trying to end her struggle for survival. Ada has now to fight with her own weapons. She will only prosper by her own merits. But two questions emerge. Do they exist? Are they better than Java’s? Our opinion is that they do exist, and are not matched by any other programming language

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In this paper, we present some of the fault tolerance management mechanisms being implemented in the Multi-μ architecture, namely its support for replica non-determinism. In this architecture, fault tolerance is achieved by node active replication, with software based replica management and fault tolerance transparent algorithms. A software layer implemented between the application and the real-time kernel, the Fault Tolerance Manager (FTManager), is the responsible for the transparent incorporation of the fault tolerance mechanisms The active replication model can be implemented either imposing replica determinism or keeping replica consistency at critical points, by means of interactive agreement mechanisms. One of the Multi-μ architecture goals is to identify such critical points, relieving the underlying system from performing the interactive agreement in every Ada dispatching point.

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This paper presents an architecture (Multi-μ) being implemented to study and develop software based fault tolerant mechanisms for Real-Time Systems, using the Ada language (Ada 95) and Commercial Off-The-Shelf (COTS) components. Several issues regarding fault tolerance are presented and mechanisms to achieve fault tolerance by software active replication in Ada 95 are discussed. The Multi-μ architecture, based on a specifically proposed Fault Tolerance Manager (FTManager), is then described. Finally, some considerations are made about the work being done and essential future developments.

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Classical lock-based concurrency control does not scale with current and foreseen multi-core architectures, opening space for alternative concurrency control mechanisms. The concept of transactions executing concurrently in isolation with an underlying mechanism maintaining a consistent system state was already explored in fault-tolerant and distributed systems, and is currently being explored by transactional memory, this time being used to manage concurrent memory access. In this paper we discuss the use of Software Transactional Memory (STM), and how Ada can provide support for it. Furthermore, we draft a general programming interface to transactional memory, supporting future implementations of STM oriented to real-time systems.

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Over the last three decades, computer architects have been able to achieve an increase in performance for single processors by, e.g., increasing clock speed, introducing cache memories and using instruction level parallelism. However, because of power consumption and heat dissipation constraints, this trend is going to cease. In recent times, hardware engineers have instead moved to new chip architectures with multiple processor cores on a single chip. With multi-core processors, applications can complete more total work than with one core alone. To take advantage of multi-core processors, parallel programming models are proposed as promising solutions for more effectively using multi-core processors. This paper discusses some of the existent models and frameworks for parallel programming, leading to outline a draft parallel programming model for Ada.

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Multiprocessors, particularly in the form of multicores, are becoming standard building blocks for executing reliable software. But their use for applications with hard real-time requirements is non-trivial. Well-known realtime scheduling algorithms in the uniprocessor context (Rate-Monotonic [1] or Earliest-Deadline-First [1]) do not perform well on multiprocessors. For this reason the scientific community in the area of real-time systems has produced new algorithms specifically for multiprocessors. In the meanwhile, a proposal [2] exists for extending the Ada language with new basic constructs which can be used for implementing new algorithms for real-time scheduling; the family of task splitting algorithms is one of them which was emphasized in the proposal [2]. Consequently, assessing whether existing task splitting multiprocessor scheduling algorithms can be implemented with these constructs is paramount. In this paper we present a list of state-of-art task-splitting multiprocessor scheduling algorithms and, for each of them, we present detailed Ada code that uses the new constructs.

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As electronic devices get smaller and more complex, dependability assurance is becoming fundamental for many mission critical computer based systems. This paper presents a case study on the possibility of using the on-chip debug infrastructures present in most current microprocessors to execute real time fault injection campaigns. The proposed methodology is based on a debugger customized for fault injection and designed for maximum flexibility, and consists of injecting bit-flip type faults on memory elements without modifying or halting the target application. The debugger design is easily portable and applicable to different architectures, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.

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Dissertação apresentada na Faculdade de Ciências e Engenharia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores