Paleomagnetic properties of igneous rocks from several DSDP and ODP sites, western Pacific

Oceanic basalts and other related igneous rocks are considered excellent recorders of the Earth's paleomagnetic field. Consequently, basalt core paleomagnetic data are valuable for the constraints they provide on plate tectonic motions, especially for oceanic plates such as the Pacific. Unfortunately, few Deep Sea Drilling Project (DSDP) and Ocean Drilling Program (ODP) boreholes have been cored very deeply into the ocean crust. The result is that there are only a few sites at which a large enough number of basalt flows have been cored to properly average secular variation (e.g., Kono, 1980, doi:10.2973/dsdp.proc.55.135.1980; Cox and Gordon, 1984, doi:10.1029/RG022i001p00047). Furthermore, there are a number of sites where basaltic core samples were retrieved but the cores were not measured. Often this occurs because leg scientists had more important sections to work on, or the section was ignored because it was too short to record enough time to average secular variation and obtain a reliable paleolatitude. Even though it may not be possible to determine a precise paleolatitude from such short sections, measurements from a small number of flows are important because they can be combined with other coeval paleomagnetic data from the same plate to calculate a paleomagnetic pole (Gordon and Cox, 1980, doi:10.1111/j.1365-246X.1980.tb02642.x; Cox and Gordon, 1984, doi:10.1029/RG022i001p00047). For this reason, I obtained samples for paleomagnetic measurements from eight Pacific sites (169, 170, 171, 581, 597, 800, 803, and 865), most of which have not been previously measured for paleomagnetism.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

Revista Cultura Económica, 2014, Año XXXII nº 88 (número completo)

Contenido: Editorial -- Artículos: El discernimiento espiritual en la toma de decisiones / Luk Bouckaert -- El redescubrimiento de la filosofía personalista de Jacques Maritain / Opdebeeck, Henrik -- Emprendedorismo guiado por la espiritualidad / Zsolnai, Laszlo -- ¿Podemos formar líderes responsables? / de Bettignies, Henri Claude -- La concepción de la sabiduría según los managers / Thompson, Mike -- Reseñas de libros