On-chip Monitoring: A Light-Weight Interconnection Network Approach

Current nanometer technologies are subjected to several adverse effects that seriously impact the yield and performance of integrated circuits. Such is the case of within-die parameters uncertainties, varying workload conditions, aging, temperature, etc. Monitoring, calibration and dynamic adaptation have appeared as promising solutions to these issues and many kinds of monitors have been presented recently. In this scenario, where systems with hundreds of monitors of different types have been proposed, the need for light-weight monitoring networks has become essential. In this work we present a light-weight network architecture based on digitization resource sharing of nodes that require a time-to-digital conversion. Our proposal employs a single wire interface, shared among all the nodes in the network, and quantizes the time domain to perform the access multiplexing and transmit the information. It supposes a 16% improvement in area and power consumption compared to traditional approaches.

Desarrollo de un datalink con el chip CC1110 de Texas Instruments para UAVs

Se trata de estudiar el comportamiento de un sistema basado en el chip CC1110 de Texas Instruments, para aplicaciones inalámbricas. Los dispositivos basados en este tipo de chips tienen actualmente gran profusión, dada la demanda cada vez mayor de aplicaciones de gestión y control inalámbrico. Por ello, en la primera parte del proyecto se presenta el estado del arte referente a este aspecto, haciendo mención a los sistemas operativos embebidos, FPGAs, etc. También se realiza una introducción sobre la historia de los aviones no tripulados, que son el vehículo elegido para el uso del enlace de datos. En una segunda parte se realiza el estudio del dispositivo mediante una placa de desarrollo, verificando y comprobando mediante el software suministrado, el alcance del mismo. Cabe resaltar en este punto que el control con la placa mencionada se debe hacer mediante programación de bajo nivel (lenguaje C), lo que aporta gran versatilidad a las aplicaciones que se pueden desarrollar. Por ello, en una tercera parte se realiza un programa funcional, basado en necesidades aportadas por la empresa con la que se colabora en el proyecto (INDRA). Este programa es realizado sobre el entorno de Matlab, muy útil para este tipo de aplicaciones, dada su versatilidad y gran capacidad de cálculo con variables. Para terminar, con la realización de dichos programas, se realizan pruebas específicas para cada uno de ellos, realizando pruebas de campo en algunas ocasiones, con vehículos los más similares a los del entorno real en el que se prevé utilizar. Como implementación al programa realizado, se incluye un manual de usuario con un formato muy gráfico, para que la toma de contacto se realice de una manera rápida y sencilla. Para terminar, se plantean líneas futuras de aplicación del sistema, conclusiones, presupuesto y un anexo con los códigos de programación más importantes. Abstract In this document studied the system behavior based on chip CC1110 of Texas Instruments, for wireless applications. These devices currently have profusion. Right the increasing demand for control and management wireless applications. In the first part of project presents the state of art of this aspect, with reference to the embedded systems, FPGAs, etc. It also makes a history introduction of UAVs, which are the vehicle for use data link. In the second part is studied the device through development board, verifying and checking with provided software the scope. The board programming is C language; this gives a good versatility to develop applications. Thus, in third part performing a functionally program, it based on requirements provided by company with which it collaborates, INDRA Company. This program is developed with Matlab, very useful for such applications because of its versatility and ability to use variables. Finally, with the implementation of such programs, specific tests are performed for each of them, field tests are performed in several cases, and vehicles used for this are the most similar to the actual environment plain to use. Like implementing with the program made, includes a graphical user manual, so your understanding is conducted quickly and easily. Ultimately, present future targets for system applications, conclusions, budget and annex of the most important programming codes.

On-Chip Thermal Monitoring: Design, Placement and Interconnection of Temperature Sensors

La temperatura es una preocupación que juega un papel protagonista en el diseño de circuitos integrados modernos. El importante aumento de las densidades de potencia que conllevan las últimas generaciones tecnológicas ha producido la aparición de gradientes térmicos y puntos calientes durante el funcionamiento normal de los chips. La temperatura tiene un impacto negativo en varios parámetros del circuito integrado como el retardo de las puertas, los gastos de disipación de calor, la fiabilidad, el consumo de energía, etc. Con el fin de luchar contra estos efectos nocivos, la técnicas de gestión dinámica de la temperatura (DTM) adaptan el comportamiento del chip en función en la información que proporciona un sistema de monitorización que mide en tiempo de ejecución la información térmica de la superficie del dado. El campo de la monitorización de la temperatura en el chip ha llamado la atención de la comunidad científica en los últimos años y es el objeto de estudio de esta tesis. Esta tesis aborda la temática de control de la temperatura en el chip desde diferentes perspectivas y niveles, ofreciendo soluciones a algunos de los temas más importantes. Los niveles físico y circuital se cubren con el diseño y la caracterización de dos nuevos sensores de temperatura especialmente diseñados para los propósitos de las técnicas DTM. El primer sensor está basado en un mecanismo que obtiene un pulso de anchura variable dependiente de la relación de las corrientes de fuga con la temperatura. De manera resumida, se carga un nodo del circuito y posteriormente se deja flotando de tal manera que se descarga a través de las corrientes de fugas de un transistor; el tiempo de descarga del nodo es la anchura del pulso. Dado que la anchura del pulso muestra una dependencia exponencial con la temperatura, la conversión a una palabra digital se realiza por medio de un contador logarítmico que realiza tanto la conversión tiempo a digital como la linealización de la salida. La estructura resultante de esta combinación de elementos se implementa en una tecnología de 0,35 _m. El sensor ocupa un área muy reducida, 10.250 nm2, y consume muy poca energía, 1.05-65.5nW a 5 muestras/s, estas cifras superaron todos los trabajos previos en el momento en que se publicó por primera vez y en el momento de la publicación de esta tesis, superan a todas las implementaciones anteriores fabricadas en el mismo nodo tecnológico. En cuanto a la precisión, el sensor ofrece una buena linealidad, incluso sin calibrar; se obtiene un error 3_ de 1,97oC, adecuado para tratar con las aplicaciones de DTM. Como se ha explicado, el sensor es completamente compatible con los procesos de fabricación CMOS, este hecho, junto con sus valores reducidos de área y consumo, lo hacen especialmente adecuado para la integración en un sistema de monitorización de DTM con un conjunto de monitores empotrados distribuidos a través del chip. Las crecientes incertidumbres de proceso asociadas a los últimos nodos tecnológicos comprometen las características de linealidad de nuestra primera propuesta de sensor. Con el objetivo de superar estos problemas, proponemos una nueva técnica para obtener la temperatura. La nueva técnica también está basada en las dependencias térmicas de las corrientes de fuga que se utilizan para descargar un nodo flotante. La novedad es que ahora la medida viene dada por el cociente de dos medidas diferentes, en una de las cuales se altera una característica del transistor de descarga |la tensión de puerta. Este cociente resulta ser muy robusto frente a variaciones de proceso y, además, la linealidad obtenida cumple ampliamente los requisitos impuestos por las políticas DTM |error 3_ de 1,17oC considerando variaciones del proceso y calibrando en dos puntos. La implementación de la parte sensora de esta nueva técnica implica varias consideraciones de diseño, tales como la generación de una referencia de tensión independiente de variaciones de proceso, que se analizan en profundidad en la tesis. Para la conversión tiempo-a-digital, se emplea la misma estructura de digitalización que en el primer sensor. Para la implementación física de la parte de digitalización, se ha construido una biblioteca de células estándar completamente nueva orientada a la reducción de área y consumo. El sensor resultante de la unión de todos los bloques se caracteriza por una energía por muestra ultra baja (48-640 pJ) y un área diminuta de 0,0016 mm2, esta cifra mejora todos los trabajos previos. Para probar esta afirmación, se realiza una comparación exhaustiva con más de 40 propuestas de sensores en la literatura científica. Subiendo el nivel de abstracción al sistema, la tercera contribución se centra en el modelado de un sistema de monitorización que consiste de un conjunto de sensores distribuidos por la superficie del chip. Todos los trabajos anteriores de la literatura tienen como objetivo maximizar la precisión del sistema con el mínimo número de monitores. Como novedad, en nuestra propuesta se introducen nuevos parámetros de calidad aparte del número de sensores, también se considera el consumo de energía, la frecuencia de muestreo, los costes de interconexión y la posibilidad de elegir diferentes tipos de monitores. El modelo se introduce en un algoritmo de recocido simulado que recibe la información térmica de un sistema, sus propiedades físicas, limitaciones de área, potencia e interconexión y una colección de tipos de monitor; el algoritmo proporciona el tipo seleccionado de monitor, el número de monitores, su posición y la velocidad de muestreo _optima. Para probar la validez del algoritmo, se presentan varios casos de estudio para el procesador Alpha 21364 considerando distintas restricciones. En comparación con otros trabajos previos en la literatura, el modelo que aquí se presenta es el más completo. Finalmente, la última contribución se dirige al nivel de red, partiendo de un conjunto de monitores de temperatura de posiciones conocidas, nos concentramos en resolver el problema de la conexión de los sensores de una forma eficiente en área y consumo. Nuestra primera propuesta en este campo es la introducción de un nuevo nivel en la jerarquía de interconexión, el nivel de trillado (o threshing en inglés), entre los monitores y los buses tradicionales de periféricos. En este nuevo nivel se aplica selectividad de datos para reducir la cantidad de información que se envía al controlador central. La idea detrás de este nuevo nivel es que en este tipo de redes la mayoría de los datos es inútil, porque desde el punto de vista del controlador sólo una pequeña cantidad de datos |normalmente sólo los valores extremos| es de interés. Para cubrir el nuevo nivel, proponemos una red de monitorización mono-conexión que se basa en un esquema de señalización en el dominio de tiempo. Este esquema reduce significativamente tanto la actividad de conmutación sobre la conexión como el consumo de energía de la red. Otra ventaja de este esquema es que los datos de los monitores llegan directamente ordenados al controlador. Si este tipo de señalización se aplica a sensores que realizan conversión tiempo-a-digital, se puede obtener compartición de recursos de digitalización tanto en tiempo como en espacio, lo que supone un importante ahorro de área y consumo. Finalmente, se presentan dos prototipos de sistemas de monitorización completos que de manera significativa superan la características de trabajos anteriores en términos de área y, especialmente, consumo de energía. Abstract Temperature is a first class design concern in modern integrated circuits. The important increase in power densities associated to recent technology evolutions has lead to the apparition of thermal gradients and hot spots during run time operation. Temperature impacts several circuit parameters such as speed, cooling budgets, reliability, power consumption, etc. In order to fight against these negative effects, dynamic thermal management (DTM) techniques adapt the behavior of the chip relying on the information of a monitoring system that provides run-time thermal information of the die surface. The field of on-chip temperature monitoring has drawn the attention of the scientific community in the recent years and is the object of study of this thesis. This thesis approaches the matter of on-chip temperature monitoring from different perspectives and levels, providing solutions to some of the most important issues. The physical and circuital levels are covered with the design and characterization of two novel temperature sensors specially tailored for DTM purposes. The first sensor is based upon a mechanism that obtains a pulse with a varying width based on the variations of the leakage currents on the temperature. In a nutshell, a circuit node is charged and subsequently left floating so that it discharges away through the subthreshold currents of a transistor; the time the node takes to discharge is the width of the pulse. Since the width of the pulse displays an exponential dependence on the temperature, the conversion into a digital word is realized by means of a logarithmic counter that performs both the timeto- digital conversion and the linearization of the output. The structure resulting from this combination of elements is implemented in a 0.35_m technology and is characterized by very reduced area, 10250 nm2, and power consumption, 1.05-65.5 nW at 5 samples/s, these figures outperformed all previous works by the time it was first published and still, by the time of the publication of this thesis, they outnumber all previous implementations in the same technology node. Concerning the accuracy, the sensor exhibits good linearity, even without calibration it displays a 3_ error of 1.97oC, appropriate to deal with DTM applications. As explained, the sensor is completely compatible with standard CMOS processes, this fact, along with its tiny area and power overhead, makes it specially suitable for the integration in a DTM monitoring system with a collection of on-chip monitors distributed across the chip. The exacerbated process fluctuations carried along with recent technology nodes jeop-ardize the linearity characteristics of the first sensor. In order to overcome these problems, a new temperature inferring technique is proposed. In this case, we also rely on the thermal dependencies of leakage currents that are used to discharge a floating node, but now, the result comes from the ratio of two different measures, in one of which we alter a characteristic of the discharging transistor |the gate voltage. This ratio proves to be very robust against process variations and displays a more than suficient linearity on the temperature |1.17oC 3_ error considering process variations and performing two-point calibration. The implementation of the sensing part based on this new technique implies several issues, such as the generation of process variations independent voltage reference, that are analyzed in depth in the thesis. In order to perform the time-to-digital conversion, we employ the same digitization structure the former sensor used. A completely new standard cell library targeting low area and power overhead is built from scratch to implement the digitization part. Putting all the pieces together, we achieve a complete sensor system that is characterized by ultra low energy per conversion of 48-640pJ and area of 0.0016mm2, this figure outperforms all previous works. To prove this statement, we perform a thorough comparison with over 40 works from the scientific literature. Moving up to the system level, the third contribution is centered on the modeling of a monitoring system consisting of set of thermal sensors distributed across the chip. All previous works from the literature target maximizing the accuracy of the system with the minimum number of monitors. In contrast, we introduce new metrics of quality apart form just the number of sensors; we consider the power consumption, the sampling frequency, the possibility to consider different types of monitors and the interconnection costs. The model is introduced in a simulated annealing algorithm that receives the thermal information of a system, its physical properties, area, power and interconnection constraints and a collection of monitor types; the algorithm yields the selected type of monitor, the number of monitors, their position and the optimum sampling rate. We test the algorithm with the Alpha 21364 processor under several constraint configurations to prove its validity. When compared to other previous works in the literature, the modeling presented here is the most complete. Finally, the last contribution targets the networking level, given an allocated set of temperature monitors, we focused on solving the problem of connecting them in an efficient way from the area and power perspectives. Our first proposal in this area is the introduction of a new interconnection hierarchy level, the threshing level, in between the monitors and the traditional peripheral buses that applies data selectivity to reduce the amount of information that is sent to the central controller. The idea behind this new level is that in this kind of networks most data are useless because from the controller viewpoint just a small amount of data |normally extreme values| is of interest. To cover the new interconnection level, we propose a single-wire monitoring network based on a time-domain signaling scheme that significantly reduces both the switching activity over the wire and the power consumption of the network. This scheme codes the information in the time domain and allows a straightforward obtention of an ordered list of values from the maximum to the minimum. If the scheme is applied to monitors that employ TDC, digitization resource sharing is achieved, producing an important saving in area and power consumption. Two prototypes of complete monitoring systems are presented, they significantly overcome previous works in terms of area and, specially, power consumption.

Microfabrication processes for microfluidic devices on a single laser Workstation: direct writing lithography on SU-8, laser ablation on polymers and mask manufacturing

We demonstrate the capability of a laser micromachining workstation for cost-effective manufacturing of a variety of microfluidic devices, including SU-8 microchannels on silicon wafers and 3D complex structures made on polyimide Kapton® or poly carbonate (PC). The workstation combines a KrF excimer laser at 248 nm and a Nd3+:YVO4 DPSS with a frequency tripled at 355 nm with a lens magnification 10X, both lasers working at a pulsed regime with nanoseconds (ns) pulse duration. Workstation also includes a high-resolution motorized XYZ-tilt axis (~ 1 um / axis) and a Through The Lens (TTL) imaging system for a high accurate positioning over a 120 x 120 mm working area. We have surveyed different fabrication techniques: direct writing lithography,mask manufacturing for contact lithography and polymer laser ablation for complex 3D devices, achieving width channels down to 13μ m on 50μ m SU-8 thickness using direct writing lithography, and width channels of 40 μm for polyimide on SiO2 plate. Finally, we have tested the use of some devices for capillary chips measuring the flow speed for liquids with different viscosities. As a result, we have characterized the presence of liquid in the channel by interferometric microscopy.

Using three-dimensional microfluidic networks for solving computationally hard problems

This paper describes the design of a parallel algorithm that uses moving fluids in a three-dimensional microfluidic system to solve a nondeterministically polynomial complete problem (the maximal clique problem) in polynomial time. This algorithm relies on (i) parallel fabrication of the microfluidic system, (ii) parallel searching of all potential solutions by using fluid flow, and (iii) parallel optical readout of all solutions. This algorithm was implemented to solve the maximal clique problem for a simple graph with six vertices. The successful implementation of this algorithm to compute solutions for small-size graphs with fluids in microchannels is not useful, per se, but does suggest broader application for microfluidics in computation and control.

Desenvolvimento e caracterização do filtro óptico de interferência variável para detectores de alta resolução espectral e biossensores.

O presente trabalho está fundamentado no desenvolvimento de uma metodologia e/ou uma tecnologia de obtenção e caracterização de filtros ópticos de interferência de banda passante variável [C.M. da Silva, 2010] e de banda de corte variáveis, constituídos por refletores dielétricos multicamadas de filmes finos intercalados por cavidades de Fabry-Perot não planares com espessuras linearmente variáveis, que apresentam a propriedade do deslocamento linear da transmitância máxima espectral em função da posição, isto é, um Filtro de Interferência Variável (FIV). Este método apresenta novas e abrangentes possibilidades de confecção de filtros ópticos de interferência variável: lineares ou em outras formas desejadas, de comprimento de onda de corte variável (passa baixa ou alta) e filtros de densidade neutra variável, através da deposição de metais, além de aplicações em uma promissora e nova área de pesquisa na deposição de filmes finos não uniformes. A etapa inicial deste desenvolvimento foi o estudo da teoria dos filtros ópticos dielétricos de interferência para projetar e construir um filtro óptico banda passante convencional de um comprimento de onda central com camadas homogêneas. A etapa seguinte, com base na teoria óptica dos filmes finos já estabelecida, foi desenvolver a extensão destes conhecimentos para determinar que a variação da espessura em um perfil inclinado e linear da cavidade entre os refletores de Bragg é o principal parâmetro para produzir o deslocamento espacial da transmitância espectral, possibilitando o uso de técnicas especiais para se obter uma variação em faixas de bandas de grande amplitude, em um único filtro. Um trabalho de modelagem analítica e análise de tolerância de espessuras dos filmes depositados foram necessários para a seleção da estratégia do \"mascaramento\" seletivo do material evaporado formado na câmara e-Beam (elétron-Beam) com o objetivo da obtenção do filtro espectral linear variável de características desejadas. Para tanto, de acordo com os requisitos de projeto, foram necessárias adaptações em uma evaporadora por e-Beam para receber um obliterador mecânico especialmente projetado para compatibilizar os parâmetros das técnicas convencionais de deposição com o objetivo de se obter um perfil inclinado, perfil este previsto em processos de simulação para ajustar e calibrar a geometria do obliterador e se obter um filme depositado na espessura, conformação e disposição pretendidos. Ao final destas etapas de modelagem analítica, simulação e refinamento recorrente, foram determinados os parâmetros de projeto para obtenção de um determinado FIV (Filtro de Interferência Variável) especificado. Baseadas nos FIVs muitas aplicações são emergentes: dispositivos multi, hiper e ultra espectral para sensoriamento remoto e análise ambiental, sistemas Lab-on-Chip, biossensores, detectores chip-sized, espectrofotometria de fluorescência on-chip, detectores de deslocamento de comprimento de onda, sistemas de interrogação, sistemas de imageamento espectral, microespectrofotômetros e etc. No escopo deste trabalho se pretende abranger um estudo de uma referência básica do emprego do (FIV) filtro de interferência variável como detector de varredura de comprimento de ondas em sensores biológicos e químicos compatível com pós processamento CMOS. Um sistema básico que é constituído por um FIV montado sobre uma matriz de sensores ópticos conectada a um módulo eletrônico dedicado a medir a intensidade da radiação incidente e as bandas de absorção das moléculas presentes em uma câmara de detecção de um sistema próprio de canais de microfluidos, configurando-se em um sistema de aquisição e armazenamento de dados (DAS), é proposto para demonstrar as possibilidades do FIV e para servir de base para estudos exploratórios das suas diversas potencialidades que, entre tantas, algumas são mencionadas ao longo deste trabalho. O protótipo obtido é capaz de analisar fluidos químicos ou biológicos e pode ser confrontado com os resultados obtidos por equipamentos homologados de uso corrente.

Modelagem e simulação de redes em chip sem fio.

O paradigma das redes em chip (NoCs) surgiu a fim de permitir alto grau de integração entre vários núcleos de sistemas em chip (SoCs), cuja comunicação é tradicionalmente baseada em barramentos. As NoCs são definidas como uma estrutura de switches e canais ponto a ponto que interconectam núcleos de propriedades intelectuais (IPs) de um SoC, provendo uma plataforma de comunicação entre os mesmos. As redes em chip sem fio (WiNoCs) são uma abordagem evolucionária do conceito de rede em chip (NoC), a qual possibilita a adoção dos mecanismos de roteamento das NoCs com o uso de tecnologias sem fio, propondo a otimização dos fluxos de tráfego, a redução de conectores e a atuação em conjunto com as NoCs tradicionais, reduzindo a carga nos barramentos. O uso do roteamento dinâmico dentro das redes em chip sem fio permite o desligamento seletivo de partes do hardware, o que reduz a energia consumida. Contudo, a escolha de onde empregar um link sem fio em uma NoC é uma tarefa complexa, dado que os nós são pontes de tráfego os quais não podem ser desligados sem potencialmente quebrar uma rota preestabelecida. Além de fornecer uma visão sobre as arquiteturas de NoCs e do estado da arte do paradigma emergente de WiNoC, este trabalho também propõe um método de avaliação baseado no já consolidado simulador ns-2, cujo objetivo é testar cenários híbridos de NoC e WiNoC. A partir desta abordagem é possível avaliar diferentes parâmetros das WiNoCs associados a aspectos de roteamento, aplicação e número de nós envolvidos em redes hierárquicas. Por meio da análise de tais simulações também é possível investigar qual estratégia de roteamento é mais recomendada para um determinado cenário de utilização, o que é relevante ao se escolher a disposição espacial dos nós em uma NoC. Os experimentos realizados são o estudo da dinâmica de funcionamento dos protocolos ad hoc de roteamento sem fio em uma topologia hierárquica de WiNoC, seguido da análise de tamanho da rede e dos padrões de tráfego na WiNoC.

Russian gas industry - current condition and prospects; New regional 'in-security' system in Central Asia; Caspian oil and gas: the facts at the end of the year 2000. OSW Study 1/2001

Russian gas industry: The current condition of the gas industry is one of the most crucial factors influencing the Russian state·s functioning, internal situation and international position. Not only is gas the principal energy resource in Russia, it also subsidises other sectors of the economy. Status of the main European gas exporter strengthens also Russia's importance in the international arena. New regional in-security: Ten years have passed since the Central Asian states declared their independence, but their relationship with Russia still remains close, and the latter treats them as its exclusive zone of influence. A crucial reason for keeping Central Asia within the orbit of Moscow·s influence is the fact that Russia exercises control over the most important transport routes out of the region of raw materials for the power industry, on which the economic development of Asia depends on. But this is the only manifestation of Central Asia·s economic dependence on Russia. Moscow lacks solid economic instruments (i.e. investment input or power industry dependence) to shape the situation in the region. Caspian oil and gas: Caspian stocks of energy resources are not, and most probably will not be, of any great significance on the world scale. Nevertheless it is the Caspian region which will have the opportunity to become an oil exporter which will reduce the dependence of the European countries on Arabian oil, and which will guarantee Russia the quantities of gas which are indispensable both for meeting its internal demands and for maintaining its current level of export. For Azerbaijan, Kazakhstan and Turkmenistan, the confirmation of the existence of successive oil strata is not only an opportunity to increase income, but also an additional bargaining chip in the game for the future of the whole region. The stake in this game is the opportunity to limit the economic, and by extension the political influences of Russia in the region.

Improving the Manufacturability of Active Microfluidic Devices using Stereolithography (SL)

Thesis (Master's)--University of Washington, 2016-06

Ultra small integrated optical fiber sensing system

This paper introduces a revolutionary way to interrogate optical fiber sensors based on fiber Bragg gratings (FBGs) and to integrate the necessary driving optoelectronic components with the sensor elements. Low-cost optoelectronic chips are used to interrogate the optical fibers, creating a portable dynamic sensing system as an alternative for the traditionally bulky and expensive fiber sensor interrogation units. The possibility to embed these laser and detector chips is demonstrated resulting in an ultra thin flexible optoelectronic package of only 40 µm, provided with an integrated planar fiber pigtail. The result is a fully embedded flexible sensing system with a thickness of only 1 mm, based on a single Vertical-Cavity Surface-Emitting Laser (VCSEL), fiber sensor and photodetector chip. Temperature, strain and electrodynamic shaking tests have been performed on our system, not limited to static read-out measurements but dynamically reconstructing full spectral information datasets.

Exploring value-added benefits to enhance wider adoption of chipless RFID system

Radio-frequency identification technology (RFID) is a popular modern technology proven to deliver a range of value-added benefits to achieve system and operational efficiency, as well as cost-effectiveness. The operational characteristics of RFID outperform barcodes in many aspects. Despite its well-perceived benefits, a definite rationale for larger scale adoption is still not so promising. One of the key reasons is high implementation cost, especially the cost of tags for applications involving item-level tagging. This has resulted in the development of chipless RFID tags which cost much less than conventional chip-based tags. Despite the much lower tag cost, the uptake of chipless RFID system in the market is still not as widespread as predicted by RFID experts. This chapter explores the value-added applications of chipless RFID system to promote wider adoption. The chipless technology's technical and operational characteristics, benefits, limitations and current uses will also be examined. The merit of this chapter is to contribute fresh propositions to the promising applications of chipless RFID to increase its adoption in the industries that are currently not (or less popular in) utilising it, such as retail, logistics, manufacturing, healthcare, and service sectors. © 2013, IGI Global.

Ultra small integrated optical fiber sensing system

This paper introduces a revolutionary way to interrogate optical fiber sensors based on fiber Bragg gratings (FBGs) and to integrate the necessary driving optoelectronic components with the sensor elements. Low-cost optoelectronic chips are used to interrogate the optical fibers, creating a portable dynamic sensing system as an alternative for the traditionally bulky and expensive fiber sensor interrogation units. The possibility to embed these laser and detector chips is demonstrated resulting in an ultra thin flexible optoelectronic package of only 40 µm, provided with an integrated planar fiber pigtail. The result is a fully embedded flexible sensing system with a thickness of only 1 mm, based on a single Vertical-Cavity Surface-Emitting Laser (VCSEL), fiber sensor and photodetector chip. Temperature, strain and electrodynamic shaking tests have been performed on our system, not limited to static read-out measurements but dynamically reconstructing full spectral information datasets.

The development of a novel Bio-MEMS filtration chip for the separation of specific cells in fluid suspension

In the clinical/microbiological laboratory there are currently several ways of separating specific cells from a fluid suspension. Conventionally cells can be separated based on size, density, electrical charge, light-scattering properties, and antigenic surface properties. Separating cells using these parameters can require complex technologies and specialist equipment. This paper proposes new Bio-MEMS (microelectromechanical systems) filtration chips manufactured using deep reactive ion etching (DRIE) technology that, when used in conjunction with an optical microscope and a syringe, can filter and grade cells for size without the requirement for additional expensive equipment. These chips also offer great versatility in terms of design and their low cost allows them to be disposable, eliminating sample contamination. The pumping mechanism, unlike many other current filtration techniques, leaves samples mechanically and chemically undamaged. In this paper the principles behind harnessing passive pumping are explored, modelled, and validated against empirical data, and their integration into a microfluidic device to separate cells from a mixed population suspension is described. The design, means of manufacture, and results from preliminary tests are also presented. © IMechE 2007.

Microfluidic-controlled manufacture of liposomes for the solubilisation of a poorly water soluble drug

Besides their well-described use as delivery systems for water-soluble drugs, liposomes have the ability to act as a solubilizing agent for drugs with low aqueous solubility. However, a key limitation in exploiting liposome technology is the availability of scalable, low-cost production methods for the preparation of liposomes. Here we describe a new method, using microfluidics, to prepare liposomal solubilising systems which can incorporate low solubility drugs (in this case propofol). The setup, based on a chaotic advection micromixer, showed high drug loading (41 mol%) of propofol as well as the ability to manufacture vesicles with at prescribed sizes (between 50 and 450 nm) in a high-throughput setting. Our results demonstrate the ability of merging liposome manufacturing and drug encapsulation in a single process step, leading to an overall reduced process time. These studies emphasise the flexibility and ease of applying lab-on-a-chip microfluidics for the solubilisation of poorly water-soluble drugs.

ASIC microcontroller design of a radiation monitoring system using VHDL modeling and FPGA implementation

Three new technologies have been brought together to develop a miniaturized radiation monitoring system. The research involved (1) Investigation a new HgI$\sb2$ detector. (2) VHDL modeling. (3) FPGA implementation. (4) In-circuit Verification. The packages used included an EG&G's crystal(HgI$\sb2$) manufactured at zero gravity, the Viewlogic's VHDL and Synthesis, Xilinx's technology library, its FPGA implementation tool, and a high density device (XC4003A). The results show: (1) Reduced cycle-time between Design and Hardware implementation; (2) Unlimited Re-design and implementation using the static RAM technology; (3) Customer based design, verification, and system construction; (4) Well suited for intelligent systems. These advantages excelled conventional chip design technologies and methods in easiness, short cycle time, and price in medium sized VLSI applications. It is also expected that the density of these devices will improve radically in the near future. ^