Robust controller for an autonomous small refrigeration unit

The authors describe the constructional features of a controller for operating an autonomous refrigeration unit powered by a field of photovoltaic panels and backed up by a generator set. The controller enables three voltage levels of operation of an inverter to meet the start, run and off cycle conditions of the refrigerator compressor. The algorithm considers several input and output parameters and status signals from each subsystem of the unit to deduce a control strategy. Such units find application for storage of vaccines and life-saving medicines requiring uninterrupted refrigeration, in medical shops, rural health centres, veterinary laboratories etc.

Network Error Correction for Unit-Delay, Memory-Free Networks Using Convolutional Codes

A single source network is said to be memory-free if all of the internal nodes (those except the source and the sinks) do not employ memory but merely send linear combinations of the symbols received at their incoming edges on their outgoing edges. In this work, we introduce network-error correction for single source, acyclic, unit-delay, memory-free networks with coherent network coding for multicast. A convolutional code is designed at the source based on the network code in order to correct network- errors that correspond to any of a given set of error patterns, as long as consecutive errors are separated by a certain interval which depends on the convolutional code selected. Bounds on this interval and the field size required for constructing the convolutional code with the required free distance are also obtained. We illustrate the performance of convolutional network error correcting codes (CNECCs) designed for the unit-delay networks using simulations of CNECCs on an example network under a probabilistic error model.

Research bed for unit selection based text to speech synthesis

The paper describes a modular, unit selection based TTS framework, which can be used as a research bed for developing TTS in any new language, as well as studying the effect of changing any parameter during synthesis. Using this framework, TTS has been developed for Tamil. Synthesis database consists of 1027 phonetically rich prerecorded sentences. This framework has already been tested for Kannada. Our TTS synthesizes intelligible and acceptably natural speech, as supported by high mean opinion scores. The framework is further optimized to suit embedded applications like mobiles and PDAs. We compressed the synthesis speech database with standard speech compression algorithms used in commercial GSM phones and evaluated the quality of the resultant synthesized sentences. Even with a highly compressed database, the synthesized output is perceptually close to that with uncompressed database. Through experiments, we explored the ambiguities in human perception when listening to Tamil phones and syllables uttered in isolation,thus proposing to exploit the misperception to substitute for missing phone contexts in the database. Listening experiments have been conducted on sentences synthesized by deliberately replacing phones with their confused ones.

Role of Nonplanar Peptide Unit in Regular Polypeptide Helices - New Model for Pply-Beta-Benzyl-L-Aspartate

The effect of non-planarity of the peptide unit on helical structures stabilized by intrachain hydrogen bonds is discussed. While the present calculations generally agree with those already reported in the literature for right-handed helical structures, it is found that the most stable left-handed structure is a novel helix, called the delta-helix. Its helical parameters are close to these reported for poly-beta-benzyl-L -aspartate. Conformational energy calculations show that poly-beta-benzyl-L -aspartate with the delta-helical structure is considerably more stable than the structure it is generally believed to take up (the omega-helix) by about 15 kcal/mol-residue.

Analysis of Bandwidth-Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions

Phase-locked loops (PLLs) are necessary in applications which require grid synchronization. Presence of unbalance or harmonics in the grid voltage creates errors in the estimated frequency and angle of a PLL. The error in estimated angle has the effect of distorting the unit vectors generated by the PLL. In this paper, analytical expressions are derived which determine the error in the phase angle estimated by a PLL when there is unbalance and harmonics in the grid voltage. By using the derived expressions, the total harmonic distortion (THD) and the fundamental phase error of the unit vectors can be determined for a given PLL topology and a given level of unbalance and distortion in the grid voltage. The accuracy of the results obtained from the analytical expressions is validated with the simulation and experimental results for synchronous reference frame PLL (SRF-PLL). Based on these expressions, a new tuning method for the SRF-PLL is proposed which quantifies the tradeoff between the unit vector THD and the bandwidth of the SRF-PLL. Using this method, the exact value of the bandwidth of the SRF-PLL can be obtained for a given worst case grid voltage unbalance and distortion to have an acceptable level of unit vector THD. The tuning method for SRF-PLL is also validated experimentally.

Inference for the Component and System Lifetime Distribution of a k-unit Parallel System Based on System Data

In this paper, we consider the inference for the component and system lifetime distribution of a k-unit parallel system with independent components based on system data. The components are assumed to have identical Weibull distribution. We obtain the maximum likelihood estimates of the unknown parameters based on system data. The Fisher information matrix has been derived. We propose -expectation tolerance interval and -content -level tolerance interval for the life distribution of the system. Performance of the estimators and tolerance intervals is investigated via simulation study. A simulated dataset is analyzed for illustration.

A Novel Design Method for SOGI-PLL for Minimum Settling Time and Low Unit Vector Distortion

Phase-locked loops (PLLs) are necessary in grid connected systems to obtain information about the frequency, amplitude and phase of the grid voltage. In stationary reference frame control, the unit vectors of PLLs are used for reference generation. It is important that the PLL performance is not affected significantly when grid voltage undergoes amplitude and frequency variations. In this paper, a novel design for the popular single-phase PLL topology, namely the second-order generalized integrator (SOGI) based PLL is proposed which achieves minimum settling time during grid voltage amplitude and frequency variations. The proposed design achieves a settling time of less than 27.7 ms. This design also ensures that the unit vectors generated by this PLL have a steady state THD of less than 1% during frequency variations of the grid voltage. The design of the SOGI-PLL based on the theoretical analysis is validated by experimental results.

High Throughput, Low Latency, Memory Optimized 64K Point FFT Architecture using Novel Radix-4 Butterfly Unit

In this paper we propose a fully parallel 64K point radix-4(4) FFT processor. The radix-4(4) parallel unrolled architecture uses a novel radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. The radix-4(4) block can take all 256 inputs in parallel and can use the select control signals to generate one out of the 256 outputs. The resultant 64K point FFT processor shows significant reduction in intermediate memory but with increased hardware complexity. Compared to the state-of-art implementation 5], our architecture shows reduced latency with comparable throughput and area. The 64K point FFT architecture was synthesized using a 130nm CMOS technology which resulted in a throughput of 1.4 GSPS and latency of 47.7 mu s with a maximum clock frequency of 350MHz. When compared to 5], the latency is reduced by 303 mu s with 50.8% reduction in area.

Discovering Math APIs by Mining Unit Tests

In today's API-rich world, programmer productivity depends heavily on the programmer's ability to discover the required APIs. In this paper, we present a technique and tool, called MATHFINDER, to discover APIs for mathematical computations by mining unit tests of API methods. Given a math expression, MATHFINDER synthesizes pseudo-code to compute the expression by mapping its subexpressions to API method calls. For each subexpression, MATHFINDER searches for a method such that there is a mapping between method inputs and variables of the subexpression. The subexpression, when evaluated on the test inputs of the method under this mapping, should produce results that match the method output on a large number of tests. We implemented MATHFINDER as an Eclipse plugin for discovery of third-party Java APIs and performed a user study to evaluate its effectiveness. In the study, the use of MATHFINDER resulted in a 2x improvement in programmer productivity. In 96% of the subexpressions queried for in the study, MATHFINDER retrieved the desired API methods as the top-most result. The top-most pseudo-code snippet to implement the entire expression was correct in 93% of the cases. Since the number of methods and unit tests to mine could be large in practice, we also implement MATHFINDER in a MapReduce framework and evaluate its scalability and response time.

Mining Unit Tests for Discovery and Migration of Math APIs

Today's programming languages are supported by powerful third-party APIs. For a given application domain, it is common to have many competing APIs that provide similar functionality. Programmer productivity therefore depends heavily on the programmer's ability to discover suitable APIs both during an initial coding phase, as well as during software maintenance. The aim of this work is to support the discovery and migration of math APIs. Math APIs are at the heart of many application domains ranging from machine learning to scientific computations. Our approach, called MATHFINDER, combines executable specifications of mathematical computations with unit tests (operational specifications) of API methods. Given a math expression, MATHFINDER synthesizes pseudo-code comprised of API methods to compute the expression by mining unit tests of the API methods. We present a sequential version of our unit test mining algorithm and also design a more scalable data-parallel version. We perform extensive evaluation of MATHFINDER (1) for API discovery, where math algorithms are to be implemented from scratch and (2) for API migration, where client programs utilizing a math API are to be migrated to another API. We evaluated the precision and recall of MATHFINDER on a diverse collection of math expressions, culled from algorithms used in a wide range of application areas such as control systems and structural dynamics. In a user study to evaluate the productivity gains obtained by using MATHFINDER for API discovery, the programmers who used MATHFINDER finished their programming tasks twice as fast as their counterparts who used the usual techniques like web and code search, IDE code completion, and manual inspection of library documentation. For the problem of API migration, as a case study, we used MATHFINDER to migrate Weka, a popular machine learning library. Overall, our evaluation shows that MATHFINDER is easy to use, provides highly precise results across several math APIs and application domains even with a small number of unit tests per method, and scales to large collections of unit tests.

An Expeditious Asymmetric Synthesis of the Polyketide Unit Present in HIV-Inhibitory Depsipeptides Aetheramide A and B

The enantioselective synthesis of the polyketide unit present in depsipeptides aetheramide A and B, which possess potent HIV-inhibitory activity, is accomplished from a chiral furyl carbinol.

Design of an Automated Dispenser Unit

This paper presents our work on developing an automated micro positioner and a low cost disposable dispenser module having a disposable dispenser core. The dispenser core is made up of Polydimethylsiloxane (PDMS). Once the user specifies the dispensing location in the Graphical User Interface (GUI), the movement of the micropositioner is automatic. The design, fabrication and characterization results of the dispenser module are also presented. The dispensing experiments are performed with Di-Ethanol Amine as the working reagent. The minimum dispensed volume achieved is about 4 nL.