Unified circuit model for the polysilicon TFT

This paper proposes two methods to improve the modelling of thin film transistors (TFTs). The first involves integrating Poissons equation numerically, given a density of trap states and other relevant material parameters including a constant mobility. Theresult is conductance as a numerical function of gate voltage. The second method recognizes that the data for areal conductance found by numerical integration, may easily be found by measurement without making assumptions about the density of trap states.

A unified circuit model for the polysilicon thin film transistor

This paper describes a unified approach to modelling the polysilicon thin film transistor (TFT) for the purposes of circuit design. The approach uses accurate methods of predicting the channel conductance and then fitting the resulting data with a polynomial. Two methods are proposed to find the channel conductance: a device model and measurement. The approach is suitable because the TFT does not have a well defined threshold voltage. The polynomial conductance is then integrated generally to find the drain current and channel charge, necessary for a complete circuit model. © 1991 The Japan Society of Applied Physics.

Accurate GTO model for circuit simulations

The GTO model presented in this paper uses analytical expressions to describe the internal physics of the device. It has been implemented to run as compiled code in the SPICE simulation package and as a MAST template in the Saber simulator. A rigorous comparison of measured simulated waveforms and performance parameters (including turn-off energies) for a 3000A device is described and discussed.