928 resultados para Reconfigurable architectures
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Par une approche supramoléculaire, des architectures radiales hétéro-poly-métalliques ont été réalisées pour des applications en photosynthèse artificielle et en magnétisme moléculaire. Dans une première partie, la synthèse et la caractérisation (spectroscopie UV-vis, émission, électrochimique, DRX) de complexes de ruthénium(II), possédant une gamme de ligands polypyridines, ont été réalisées. Les calculs théoriques ont été effectués afin de soutenir l’interprétation des propriétés photophysiques. Ces complexes, présentant un certain nombre de pyridines externes, ont servi de cœur à des architectures à base de rhénium tris-carbonyles (pour les effets d’antenne), et de cobaloximes (pour les propriétés catalytiques). Les nucléarités obtenues varient de 2 à 7 selon le cœur utilisé. Ces systèmes ont été engagés dans des cycles de photo-production de dihydrogène, démontrant une meilleure efficacité que la référence du domaine, le [Ru(bpy)3]2+. La seconde partie concerne l’étude de couples de métaux de transition, construits à partir de briques polycyanométallates, ou de lanthanides pontés par des ligands oxamides. Ces approches « complexes comme ligand » puis « assemblages comme ligand » permettent d’obtenir des systèmes de haute nucléarité, présentant des propriétés de molécule-aimant ou des effets magnéto-caloriques (à base de CrNi, GdCu, DyCu). Des propriétés photomagnétiques ont été observées sur les couples RuCu et MoCu, pouvant servir de commutateurs moléculaires dans des systèmes complexes. Enfin, une structure hétéro-tétra-métallique trifonctionnelle a été obtenue contenant à la fois un commutateur MoCu, une entité molécule-aimant CuTb et un complexe de ruthénium.
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A new design for a compact electronically reconffgurable singlefeed dual frequency dual-polarized operation of a square-microstrip antenna capable of achieving tunable frequency ratios in the range 1.1 to 1.37 is proposed and experimentally studied. Varactor diodes inlegruted with the arms of the hexagonal slot and embedded in the square patch are used to tune the operating frequencies by applying reverse-bias voltage. The design has the advantage of size reduction up to 73.21% and 49.86% for the two resonant frequencies, respectively, as compared to standard rectangular patches. The antenna offers good bandwidth of 5.74% and 5.36% for the two operating frequencies. A highly simplified tuning circuitry without any transmission lines adds to the compactness of the design
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A novel design of a computer electronically reconfigurable dual frequency dual polarized single feed hexagonal slot loaded microstrip antenna in L-band is introduced in this chapter. pin diodes are used to switch the operating frequencies considerably without much affecting the radiation characteristics and gain. the antenna can work with a frequency ratio varying in the wide range from 1.2 to 1.4. the proposed design has an added advantage of size reduction up to 72.21% and 46.84% for the two resonating frequencies compared to standard rectangular patches. the design also gives considerable bandwidth of up to 2.82% and 2.42 % for the operating frequencies.
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Regional Research Laboratory
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Analog-to digital Converters (ADC) have an important impact on the overall performance of signal processing system. This research is to explore efficient techniques for the design of sigma-delta ADC,specially for multi-standard wireless tranceivers. In particular, the aim is to develop novel models and algorithms to address this problem and to implement software tools which are avle to assist the designer's decisions in the system-level exploration phase. To this end, this thesis presents a framework of techniques to design sigma-delta analog to digital converters.A2-2-2 reconfigurable sigma-delta modulator is proposed which can meet the design specifications of the three wireless communication standards namely GSM,WCDMA and WLAN. A sigma-delta modulator design tool is developed using the Graphical User Interface Development Environment (GUIDE) In MATLAB.Genetic Algorithm(GA) based search method is introduced to find the optimum value of the scaling coefficients and to maximize the dynamic range in a sigma-delta modulator.
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The design of a compact, single feed, dual frequency dual polarized and electronically reconfigurable microstrip antenna is presented in this paper. A square patch loaded with a hexagonal slot having extended slot arms constitutes the fundamental structure of the antenna. The tuning of the two resonant frequencies is realized by varying the effective electrical length of the slot arms by embedding varactor diodes across the slots. A high tuning range of 34.43% (1.037–1.394 GHz) and 9.27% (1.359–1.485 GHz) is achieved for the two operating frequencies respectively, when the bias voltage is varied from 0 to −30 V. The salient feature of this design is that it uses no matching networks even though the resonant frequencies are tuned in a wide range with good matching below −10 dB. The antenna has an added advantage of size reduction up to 80.11% and 65.69% for the two operating frequencies compared to conventional rectangular patches.
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A new electronically reconfigurable dual frequency microstrip patch antenna with highly simplified varactor tuning circuitry is presented. The proposed design allows relatively independent selection of the two operating frequencies. Tuning ranges of 7.1 and 4.1% are realised for the two resonant frequencies without the use of any matching circuits.
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In this work,we investigate novel designs of compact electronically reconfigurable dual frequency microstrip antennas with a single feed,operating mainly in L-band,without using any matching networks and complicated biasing circuitry.These antennas have been designed to operate in very popular frequency range where a great number of wireless communication applications exist.Efforts were carried out to introduce a successful,low cost reconfigurable dual-frequency microstrip antenna design to the wireless and radio frequency design community.
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Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.
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Design and study of molecular receptors capable of mimicking natural processes has found applications in basic research as well as in the development of potentially useful technologies. Of the various receptors reported, the cyclophanes are known to encapsulate guest molecules in their cavity utilizing various non–covalent interactions resulting in significant changes in their optical properties. This unique property of the cyclophanes has been widely exploited for the development of selective and sensitive probes for a variety of guest molecules including complex biomolecules. Further, the incorporation of metal centres into these systems added new possibilities for designing receptors such as the metallocyclophanes and transition metal complexes, which can target a large variety of Lewis basic functional groups that act as selective synthetic receptors. The ligands that form complexes with the metal ions, and are capable of further binding to Lewis-basic substrates through open coordination sites present in various biomolecules are particularly important as biomolecular receptors. In this context, we synthesized a few anthracene and acridine based metal complexes and novel metallocyclophanes and have investigated their photophysical and biomolecular recognition properties.
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The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers to attain higher system capacities and data rates. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.16e standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 24% to include WiMAX compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated.
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The recent trends envisage multi-standard architectures as a promising solution for the future wireless transceivers. The computationally intensive decimation filter plays an important role in channel selection for multi-mode systems. An efficient reconfigurable implementation is a key to achieve low power consumption. To this end, this paper presents a dual-mode Residue Number System (RNS) based decimation filter which can be programmed for WCDMA and 802.11a standards. Decimation is done using multistage, multirate finite impulse response (FIR) filters. These FIR filters implemented in RNS domain offers high speed because of its carry free operation on smaller residues in parallel channels. Also, the FIR filters exhibit programmability to a selected standard by reconfiguring the hardware architecture. The total area is increased only by 33% to include WLANa compared to a single mode WCDMA transceiver. In each mode, the unused parts of the overall architecture is powered down and bypassed to attain power saving. The performance of the proposed decimation filter in terms of critical path delay and area are tabulated
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Globalization is widely regarded as the rise of the borderless world. However in practice, true globalization points rather to a “spatial logic” by which globalization is manifested locally in the shape of insular space. Globalization in this sense is not merely about the creation of physical fragmentation of space but also the creation of social disintegration. This study tries to proof that global processes also create various forms of insular space leading also to specific social implications. In order to examine the problem this study looks at two cases: China’s Pearl River Delta (PRD) and Jakarta in Indonesia. The PRD case reveals three forms of insular space namely the modular, concealed and the hierarchical. The modular points to the form of enclosed factories where workers are vulnerable for human-right violations due to the absent of public control. The concealed refers to the production of insular space by subtle discrimination against certain social groups in urban space. And the hierarchical points to a production of insular space that is formed by an imbalanced population flow. The Jakarta case attempts to show more types of insularity in relation to the complexity of a mega-city which is shaped by a culture of exclusion. Those are dormant and hollow insularity. The dormant refers to the genesis of insular– radical – community from a culture of resistance. The last type, the hollow, points to the process of making a “pseudo community” where sense of community is not really developed as well as weak social relationship with its surrounding. Although global process creates various expressions of territorial insularization, however, this study finds that the “line of flight” is always present, where the border of insularity is crossed. The PRD’s produces vernacular modernization done by peasants which is less likely to be controlled by the politics of insularization. In Jakarta, the culture of insularization causes urban informalities that have no space, neither spatially nor socially; hence their state of ephemerality continues as a tactic of place-making. This study argues that these crossings possess the potential for reconciling venue to defuse the power of insularity.
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Traditionally, we've focussed on the question of how to make a system easy to code the first time, or perhaps on how to ease the system's continued evolution. But if we look at life cycle costs, then we must conclude that the important question is how to make a system easy to operate. To do this we need to make it easy for the operators to see what's going on and to then manipulate the system so that it does what it is supposed to. This is a radically different criterion for success. What makes a computer system visible and controllable? This is a difficult question, but it's clear that today's modern operating systems with nearly 50 million source lines of code are neither. Strikingly, the MIT Lisp Machine and its commercial successors provided almost the same functionality as today's mainstream sytsems, but with only 1 Million lines of code. This paper is a retrospective examination of the features of the Lisp Machine hardware and software system. Our key claim is that by building the Object Abstraction into the lowest tiers of the system, great synergy and clarity were obtained. It is our hope that this is a lesson that can impact tomorrow's designs. We also speculate on how the spirit of the Lisp Machine could be extended to include a comprehensive access control model and how new layers of abstraction could further enrich this model.
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En l’actualitat, l’electrònica digital s’està apoderant de la majoria de camps de desenvolupament, ja que ofereix un gran ventall de possibilitats que permeten fer front a gran quantitat de problemàtiques. Poc a Poc s’ha anat prescindint el màxim possible de l’electrònica analògica i en el seu lloc s’han utilitzat sistemes microprocessats, PLDs o qualsevol altre dispositiu digital, que proporciona beneficis enlluernadors davant la fatigosa tasca d’implementar una solució analògica. Tot i aquesta tendència, és inevitable la utilització de l’electrònica analògica, ja que el mon que ens envolta és l’entorn en el que han de proporcionar servei els diferents dissenys que es realitzen, i aquest entorn no és discret sinó continu. Partint d’aquest punt ben conegut hem de ser conscients que com a mínim els filtres d’entrada i sortida de senyal juntament amb els convertidors D/A A/D mai desapareixeran. Així doncs, aquests circuits analògics, de la mateixa forma que els digitals, han de ser comprovats un cop dissenyats, és en aquest apartat on el nostre projecte desenvoluparà un paper protagonista, ja que serà la eina que ha de permetre obtenir les diferents senyals característiques d’un determinat circuit, per posteriorment realitzar els tests que determinaran si es compleix el rang de correcte funcionament, i en cas de no complir, poder concretar quin paràmetre és el causant del defecte