Electrical and optical interconnects for high-performance computing

Technology scaling has enabled drastic growth in the computational and storage capacity of integrated circuits (ICs). This constant growth drives an increasing demand for high-bandwidth communication between and within ICs. In this dissertation we focus on low-power solutions that address this demand. We divide communication links into three subcategories depending on the communication distance. Each category has a different set of challenges and requirements and is affected by CMOS technology scaling in a different manner. We start with short-range chip-to-chip links for board-level communication. Next we will discuss board-to-board links, which demand a longer communication range. Finally on-chip links with communication ranges of a few millimeters are discussed.

Electrical signaling is a natural choice for chip-to-chip communication due to efficient integration and low cost. IO data rates have increased to the point where electrical signaling is now limited by the channel bandwidth. In order to achieve multi-Gb/s data rates, complex designs that equalize the channel are necessary. In addition, a high level of parallelism is central to sustaining bandwidth growth. Decision feedback equalization (DFE) is one of the most commonly employed techniques to overcome the limited bandwidth problem of the electrical channels. A linear and low-power summer is the central block of a DFE. Conventional approaches employ current-mode techniques to implement the summer, which require high power consumption. In order to achieve low-power operation we propose performing the summation in the charge domain. This approach enables a low-power and compact realization of the DFE as well as crosstalk cancellation. A prototype receiver was fabricated in 45nm SOI CMOS to validate the functionality of the proposed technique and was tested over channels with different levels of loss and coupling. Measurement results show that the receiver can equalize channels with maximum 21dB loss while consuming about 7.5mW from a 1.2V supply. We also introduce a compact, low-power transmitter employing passive equalization. The efficacy of the proposed technique is demonstrated through implementation of a prototype in 65nm CMOS. The design achieves up to 20Gb/s data rate while consuming less than 10mW.

An alternative to electrical signaling is to employ optical signaling for chip-to-chip interconnections, which offers low channel loss and cross-talk while providing high communication bandwidth. In this work we demonstrate the possibility of building compact and low-power optical receivers. A novel RC front-end is proposed that combines dynamic offset modulation and double-sampling techniques to eliminate the need for a short time constant at the input of the receiver. Unlike conventional designs, this receiver does not require a high-gain stage that runs at the data rate, making it suitable for low-power implementations. In addition, it allows time-division multiplexing to support very high data rates. A prototype was implemented in 65nm CMOS and achieved up to 24Gb/s with less than 0.4pJ/b power efficiency per channel. As the proposed design mainly employs digital blocks, it benefits greatly from technology scaling in terms of power and area saving.

As the technology scales, the number of transistors on the chip grows. This necessitates a corresponding increase in the bandwidth of the on-chip wires. In this dissertation, we take a close look at wire scaling and investigate its effect on wire performance metrics. We explore a novel on-chip communication link based on a double-sampling architecture and dynamic offset modulation technique that enables low power consumption and high data rates while achieving high bandwidth density in 28nm CMOS technology. The functionality of the link is demonstrated using different length minimum-pitch on-chip wires. Measurement results show that the link achieves up to 20Gb/s of data rate (12.5Gb/s/$\mu$m) with better than 136fJ/b of power efficiency.

Análisis de la fabricación de las tijas de una motocicleta de competición. Prototipo

[ES]Este trabajo fin de grado, TFG en adelante, consiste en el análisis de la fabricación de las tijas de una motocicleta de competición Motostudent. Se trata de conseguir fabricar las tijas de una manera óptima, tanto en que su material como el proceso de fabricación sea el más adecuado para su función siendo, además, lo más económico posible. Para llevar a cabo este trabajo es necesario conocer las cualidades que una tija debe cubrir en una motocicleta de competición. A partir de dichas cualidades se selecciona el material idóneo de entre otros muchos, estudiando las propiedades fiscas, químicas y mecánicas de cada uno de ellos. También se hará un estudio de dos alternativas de fabricación posibles, electroerosión y arranque de viruta con herramienta, para a posteriori elegir la más indicada. La idea no es construir un diseño final para la fabricación, sino un prototipo sobre el cual hacer las pruebas oportunas y posteriormente realizar cambios y mejoras para posteriores ediciones. El presente proyecto marcará las pautas de diseño y el proceso a seguir durante la fabricación de las tijas que el equipo representante de la Escuela técnica superior de Bilbao, ETSIB en adelante, empleará en la futura competición.

高功率激光装置前端系统激光脉冲的时间整形及修正技术

针对激光惯性约束聚变实验研究对高功率激光驱动器前端系统复杂时间形状种子激光脉冲的需求, 应用孔径耦合带状线集成波导整形系统设计了满足需要的前端整形激光脉冲。用一种新方法精确计算了孔径耦合带状线电脉冲整形器的耦合系数和孔径宽度的数值关系, 并针对高衬比度整形激光脉冲的需求, 提出了高衬比度双极型集成波导整形系统方案。由该系统可以得到100 ps脉冲前沿、1～3 ns脉冲宽度可调、高衬比度(大于100∶1)、光滑无纹波调制、可精确满足神光II八路及第九路装置需求的前端整形激光脉冲。

Time-frequency spectral estimation of speech

In recent years there has been a growing interest amongst the speech research community into the use of spectral estimators which circumvent the traditional quasi-stationary assumption and provide greater time-frequency (t-f) resolution than conventional spectral estimators, such as the short time Fourier power spectrum (STFPS). One distribution in particular, the Wigner distribution (WD), has attracted considerable interest. However, experimental studies have indicated that, despite its improved t-f resolution, employing the WD as the front end of speech recognition system actually reduces recognition performance; only by explicitly re-introducing t-f smoothing into the WD are recognition rates improved. In this paper we provide an explanation for these findings. By treating the spectral estimation problem as one of optimization of a bias variance trade off, we show why additional t-f smoothing improves recognition rates, despite reducing the t-f resolution of the spectral estimator. A practical adaptive smoothing algorithm is presented, whicy attempts to match the degree of smoothing introduced into the WD with the time varying quasi-stationary regions within the speech waveform. The recognition performance of the resulting adaptively smoothed estimator is found to be comparable to that of conventional filterbank estimators, yet the average temporal sampling rate of the resulting spectral vectors is reduced by around a factor of 10. © 1992.

A CMOS analogue predistortion circuit for wideband optical fibre links

The laser is a major source of nonlinearity for optical fibre communication systems. In this paper, we propose a CMOS analogue predistortion circuit to reduce laser nonlinearity for wideband optical fibre links. The circuit uses a nonlinearity having the inverse transfer characteristic of the directly modulated vertical cavity surface emitting laser (VCSEL). It is shown by post-layout simulation that the predistortion circuit shows 12dBm improvement in the optical fibre system. The optical fibre transmitter front-end with predistortion lineariser is being fabricated using the austriamicrosystems (AMS) 0.3 5μm CMOS technology.

Addressing the cognitive and social influence inhibitors during the ideation stages of technology roadmapping workshops

Technology roadmapping workshops are essentially a social mechanism for exploring, creating, shaping and implementing ideas. The front-end of a roadmapping session is based on brainstorming in order to tap into the group's diverse knowledge. The aim of this idea stimulation activity is to capture and share as many perspectives as possible across the full scope of the area of interest. The premise to such group brainstorming is that the sharing and exchange of ideas leads to cognitive stimulation resulting in a greater overall group idea generation performance in terms of the number, variety and originality of ideas. However, it must be recognized that the ideation stage in a roadmapping workshop is a complex psychosocial phenomenon with underlying cognitive and social processes. Thus, there are downsides to group interactions and these must be addressed in order to fully benefit from the power of a roadmapping workshop. This paper will highlight and discuss the key cognitive and social inhibitors involved. These include: production blocking, evaluation apprehension, free riding/social loafing, low norm setting/matching. Facilitation actions and process adjustments to counter such negative factors will be identified so as to provide a psychosocial basis for improving the running of roadmapping workshops. © 2009 PICMET.

Constrained discriminative mapping transforms for unsupervised speaker adaptation

Discriminative mapping transforms (DMTs) is an approach to robustly adding discriminative training to unsupervised linear adaptation transforms. In unsupervised adaptation DMTs are more robust to unreliable transcriptions than directly estimating adaptation transforms in a discriminative fashion. They were previously proposed for use with MLLR transforms with the associated need to explicitly transform the model parameters. In this work the DMT is extended to CMLLR transforms. As these operate in the feature space, it is only necessary to apply a different linear transform at the front-end rather than modifying the model parameters. This is useful for rapidly changing speakers/environments. The performance of DMTs with CMLLR was evaluated on the WSJ 20k task. Experimental results show that DMTs based on constrained linear transforms yield 3% to 6% relative gain over MLE transforms in unsupervised speaker adaptation. © 2011 IEEE.

Low-cost PCB-integrated 10-Gb/s optical transceiver built with a novel integration method

A novel integration method for the production of cost-effective optoelectronic printed circuit boards (OE PCBs) is presented. The proposed integration method allows fabrication of OE PCBs with manufacturing processes common to the electronics industry while enabling direct attachment of electronic components onto the board with solder reflow processes as well as board assembly with automated pick-and-place tools. The OE PCB design is based on the use of polymer multimode waveguides, end-fired optical coupling schemes, and simple electro-optic connectors, eliminating the need for additional optical components in the optical layer, such as micro-mirrors and micro-lenses. A proof-of-concept low-cost optical transceiver produced with the proposed integration method is presented. This transceiver is fabricated on a low-cost FR4 substrate, comprises a polymer Y-splitter together with the electronic circuitry of the transmitter and receiver modules and achieves error-free 10-Gb/s bidirectional data transmission. Theoretical studies on the optical coupling efficiencies and alignment tolerances achieved with the employed end-fired coupling schemes are presented while experimental results on the optical transmission characteristics, frequency response, and data transmission performance of the integrated optical links are reported. The demonstrated optoelectronic unit can be used as a front-end optical network unit in short-reach datacommunication links. © 2011-2012 IEEE.

Tandem system adaptation using multiple linear feature transforms

Adaptation to speaker and environment changes is an essential part of current automatic speech recognition (ASR) systems. In recent years the use of multi-layer percpetrons (MLPs) has become increasingly common in ASR systems. A standard approach to handling speaker differences when using MLPs is to apply a global speaker-specific constrained MLLR (CMLLR) transform to the features prior to training or using the MLP. This paper considers the situation when there are both speaker and channel, communication link, differences in the data. A more powerful transform, front-end CMLLR (FE-CMLLR), is applied to the inputs to the MLP to represent the channel differences. Though global, these FE-CMLLR transforms vary from time-instance to time-instance. Experiments on a channel distorted dialect Arabic conversational speech recognition task indicates the usefulness of adapting MLP features using both CMLLR and FE-CMLLR transforms. © 2013 IEEE.

支持JSR286规范的Portlet协作框架的设计与实现

Portlet是具有用户界面的可与用户多次交互的Web组件。随着Portal和Portlet在企业中的广泛应用，仅仅将各种应用和数据通过Portlet集成到Portal中已经不能满足用户的需求。用户希望这些应用之间能够相互协作，以利用现有应用组建新的业务流程。Portlet协作是指两个或多个Portlet进行信息交换并使用这些信息的能力。目前协作功能的实现方式可以分为两种：基于后端(back-end)的实现方式与基于前端(front-end)的实现方式。在这两种协作实现方式的基础上，本文提出了两种Portlet协作框架。 本文提出一种基于事件的Portlet前端协作模型，通过引入此模型，解决了Portlet前端协作中客户端与服务器端无法交互的困难，使协作动作由客户端和服务器端共同完成。基于此模型提供给开发者一种可扩展的协作框架，利用JavaScript技术使得协作的Portlet在客户端“相知”，协作的行为在客户端触发，Portlet获得协作数据后使用Ajax技术请求服务器端的资源，服务器端使用JSR286规范定义的资源服务接口响应用户的请求，进而动态更新界面。 当前的Portlet后端协作方式依赖于特定的Portal产品，针对这点不足，本文在JSR286规范定义的事件及共享渲染参数协作机制基础上，实现了一个Portlet后端协作框架。在该框架中协作服务使用消息队列保存待处理的消息，Portlet 容器作为中介实现发布事件的Portlet和订阅事件的Portlet之间松散耦合。Portlet监听协作事件，事件触发后调用事件协作服务发布事件，为了提高协作的并发性，事件协作服务使用多线程处理协作事件。该协作框架与JSR286规范兼容，具有良好的可移植性。 本文对这两种Portlet协作框架进行了实现，并将其应用于中科院软件所自主开发的门户产品OncePortal中。本文重构了OncePortal系统，给出了框架的体系结构与系统接口，描述了框架的各功能模块，并详细讨论了Portlet协作框架中的关键技术，包括事件协作流程的描述、事件处理过程、多级事件流等。

Multi-strip MRPCs for FOPI

During the last years FOPI has developed a new ToF system as an upgrade of the existing detector based on Multi-strip Multi-gap Resistive Plate Chambers (MMRPCs). The intention is to increase the charged Kaon identification up to a laboratory momentum of 1 GeV/c and to enhance the azimuthal detector granularity. The new ToF barrel has an active area of 5 m(2) with 2400 individual strips (900 x 1.6 mm(2)) [A. Schuttauf, et al., Nucl. Phys. B 158 (2006) 52] which are read out on both sides by a custom designed electronics [M. Ciobanu, et al., IEEE Trans. Nucl. Sci. NS-54 (4) (2007) 1201; K. Koch, et al., IEEE Trans. Nucl. Sci. NS-52(3) (2005) 745]. To reach the envisaged goal a time resolution of 100 ps is needed, at a flight path of 1-1.3 m. Due to the rare production of the K- at SIS energies the efficiency of the MMRPCs has to be above 95%. We report on measurements with the detectors and electronics from the mass production line. For this purpose we used a proton beam at 2.0 and 1.25 GeV, at rates between 0.1 and 5 kHz/cm(2) to determine the timing, efficiency and rate capability of the MMRPCs

A low noise charge sensitive preamplifier with switch control feedback resistance

In this paper, the design and analysis of a new low noise charge sensitive preamplifier for silicon strip, Si(Li), CdZnTe and CsI detectors etc. with switch control feedback resistance were described, the entire system to be built using the CMOS transistors. The circuit configuration of the CSP proposed in this paper can be adopted to develop CMOS-based Application Specific Integrated Circuit further for Front End Electronics of read-out system of nuclear physics, particle physics and astrophysics research, etc. This work is an implemented design that we succeed after a simulation to obtain a rise time less than 3ns, the output resistance less than 94 Omega and the linearity almost good.

The Compact Pulsed Hadron Source: A Design Perspective

During the past. decades, large-scale national neutron sources have been developed in Asia, Europe, and North America. Complementing such efforts, compact hadron beam complexes and neutron sources intended to serve primarily universities and industrial institutes have been proposed, and some have recently been established. Responding to the demand in China for pulsed neutron/proton-beam platforms that are dedicated to fundamental and applied research for users in multiple disciplines from materials characterization to hadron therapy and radiography to accelerator-driven sub-critical reactor systems (ADS) for nuclear waste transmutation, we have initiated the construction of a compact, yet expandable, accelerator complex-the Compact Pulsed Hadron Source (CPHS). It consists of an accelerator front-end (a high-intensity ion source, a 3-MeV radio-frequency quadrupole linac (RFQ), and a 13-MeV drift-tube linac (DTL)), a neutron target station (a beryllium target with solid methane and room-temperature water moderators/reflector), and experimental stations for neutron imaging/radiography, small-angle scattering, and proton irradiation. In the future, the CPHS may also serve as an injector to a ring for proton therapy and radiography or as the front end to an ADS test facility. In this paper, we describe the design of the CPHS technical systems and its intended operation.

中子墙探测器前端电子学研究

随着国家大科学工程兰州重离子加速器冷却储存环(HIRFL-CSR)建成，CSRm实验探测系统也正在建设当中。CSRm实验探测系统由外靶系统和内靶系统构成。外靶系统主要有γ探测器、多丝漂移室（MWDC）、ToF墙(ToF Wall)、中子墙（Neutron Wall）等探测器组成，主要用于核物理研究。其中，用于探测中子的中子墙探测器是外靶系统中的一个重要组成部分，它有252个探测单元，每一个探测器单元都要求既有很好的能量分辨，也要有很好的时间分辨，同时还要求数据获取率达到每秒几千个事件。对于这样先进的探测器和大型实验探测系统采用传统的电子学仪器和方法已经无法构成读出电子学系统，建造与之相配的读出电子学系统是极为重要的和亟待解决的工作。为此，我们设计研发适合于中子墙探测器这样的大型闪烁体探测器的前端电子学读出系统。包括三大部分：16道电荷幅度转换电路（QAC），16道时间幅度转换电路（TAC）和有效信号判断电路。本论文的主要内容如下：在第一章绪论中，介绍了论文课题的出发点以及课题的意义，并对课题的背景进行了介绍。第二章介绍我们所自行设计的中子墙探测器的特点、结构。分析了中子墙探测器的输出信号的特点以及对后续前端电子学读出系统的要求。第三章是本论文两大核心部分之一，是本论文的创新点所在。主要介绍了我们电荷幅度转换的新方法，结合通常的QAC电路方法和具体的实际情况，我们自行提出了一种新的QAC电路，包括以下几个部分：差分输入电路、电流分割、上下恒流源、门控电流积分器。我们的创新点在于，我们用上下恒流源分别代替了通常QAC中作为电流分配的电流镜像和作为电流基准的电阻，这样一来更容易得到比较稳定的偏置电流，从而能够得到更高的转换精度。第四章是本论文的另外一个核心部分，首先我们论述了核电子学时间测量的几种方法，在对它们进行对比后，结合中子墙的实际特点，我们确定了采用起停型的TAC方法。然后介绍了TAC的原理，以及具体的电路结构。第五章主要的内容是对我们整个电路的逻辑电路进行了详细的介绍，它包括16道QAC和16道TAC的积分控制信号和泄放控制信号的产生电路以及有效信号判断电路。详细论述了这些逻辑关系以及如何在CPLD实现，并且给出了仿真结果。第六章详细讨论了我们在设计PCB板时遇到的问题及其解决方法。第七章介绍了多路QAC和多路TAC主要指标及其测试方法、步骤、结果并给出了误差分析。在总结部分我们回顾了我们整个工作的过程，介绍了论文的主要成果和创新点以及对于整个CSR工程的意义。本论文的创新点： 1、提出了一种新型的QAC电路。 2、将16道QAC和16道TAC以及有效信号判断电路集成在一个插件中提高了电路的集成度，并为最终集成在一片ASIC芯片中打下坚实的基础。 3、用可编程逻辑器件代替ECL器件来构建逻辑电路，降低了功耗和成本并提高了系统的可靠性