940 resultados para ON-A-CHIP


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Surface plasmon resonance (SPR) technology and the Biacore biosensor have been widely used to measure the kinetics of biomolecular interactions in the fluid phase. In the past decade, the assay was further extended to measure reaction kinetics when two counterpart molecules are anchored on apposed surfaces. However, the cell binding kinetics has not been well quantified. Here we report development of a cellular kinetic model, combined with experimental procedures for cell binding kinetic measurements, to predict kinetic rates per cell. Human red blood cells coated with bovine serum albumin and anti-BSA monoclonal antibodies (mAbs) immobilized on the chip were used to conduct the measurements. Sensor-grams for BSA-coated RBC binding onto and debinding from the anti-BSA mAb-immobilized chip were obtained using a commercial Biacore 3000 biosensor, and analyzed with the cellular kinetic model developed. Not only did the model fit the data well, but it also predicted cellular on and off-rates as well as binding affinities from curve fitting. The dependence of flow duration, flow rate, and site density of BSA on binding kinetics was tested systematically, which further validated the feasibility and reliability of the new approach. Crown copyright (c) 2008 Published by Elsevier Inc. All rights reserved.

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A parallel plate flow chamber was used to study the interaction force between human IgG (immobilized on a chip surface as ligand) and goat anti-human IgG (immobilized on microspheres surface as receptor). First, it was demonstrated that the binding force between the microspheres and the chip surface came from the bio-specific interaction between the antigen and the antibody. Secondly, it was obtained that the critical shear rate to detach microspheres from the chip surface increases with the ligand surface concentration. Finally, two models to estimate the antigen-antibody bond strength considering bonds' positions were proposed and analyzed.

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In this paper, we studied the role of vertical component Of Surface tension of a water droplet on the deformation of membranes and microcantilevers (MCLs) widely used in lab-on-a-chip and micro-and nano-electromechanical system (MEMS/NEMS). Firstly, a membrane made of a rubber-like material, poly(dimethylsiloxane) (PDMS), was considered. The deformation was investigated using the Mooney-Rivlin (MR) model and the linear elastic constitutive relation, respectively. By comparison between the numerical solutions with two different models, we found that the simple linear elastic model is accurate enough to describe such kind of problem, which would be quite convenient for engineering applications. Furthermore, based on small-deflection beam theory, the effect of a liquid droplet on the deflection of a MCL was also studied. The free-end deflection of the MCL was investigated by considering different cases like a cylindrical droplet, a spherical droplet centered on the MCL and a spherical droplet arbitrarily positioned on the MCL. Numerical simulations demonstrated that the deflection might not be neglected, and showed good agreement with our theoretical analyses. (C) 2008 Elsevier Inc. All rights reserved.

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For efficiently cooling electronic components with high heat flux, experiments were conducted to study the flow boiling heat transfer performance of FC-72 over square silicon chips with the dimensions of 10 × 10 × 0.5 mm3. Four kinds of micro-pin-fins with the dimensions of 30 × 60, 30 × 120, 50 × 60, 50 × 120 μm2 (thickness, t × height, h) were fabricated on the chip surfaces by the dry etching technique for enhancing boiling heat transfer. A smooth surface was also tested for comparison. The experiments were made at three different fluid velocities (0.5, 1 and 2 m/s) and three different liquid subcoolings (15, 25 and 35 K). The results were compared with the previous published data of pool boiling. All micro-pin-fined surfaces show a considerable heat transfer enhancement compared with a smooth surface. Flow boiling can remarkably decrease wall superheat compared with pool boiling. At the velocities lower than 1 m/s, the micro-pin-finned surfaces show a sharp increase in heat flux with increasing wall superheat. For all surfaces, the maximum allowable heat flux, qmax, for the normal operation of LSI chips increases with fluid velocity and subcooling. For all micro-pin-finned surfaces, the wall temperature at the critical heat flux (CHF) is less than the upper limit for the reliable operation of LSI chips, 85◦C. The largest value of qmax can reach nearly 148 W/cm2 for micro-pin-finned chips with the fin height of 120 μm at the fluid velocity of 2 m/s and the liquid subcooling of 35 K. The perspectives for the boiling heat transfer experiment of the prospective micro-pin-finned sur- faces, which has been planned to be made in the Drop Tower Beijing/NMLC in the future, are also presented.

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Using neuromorphic analog VLSI techniques for modeling large neural systems has several advantages over software techniques. By designing massively-parallel analog circuit arrays which are ubiquitous in neural systems, analog VLSI models are extremely fast, particularly when local interactions are important in the computation. While analog VLSI circuits are not as flexible as software methods, the constraints posed by this approach are often very similar to the constraints faced by biological systems. As a result, these constraints can offer many insights into the solutions found by evolution. This dissertation describes a hardware modeling effort to mimic the primate oculomotor system which requires both fast sensory processing and fast motor control. A one-dimensional hardware model of the primate eye has been built which simulates the physical dynamics of the biological system. It is driven by analog VLSI circuits mimicking brainstem and cortical circuits that control eye movements. In this framework, a visually-triggered saccadic system is demonstrated which generates averaging saccades. In addition, an auditory localization system, based on the neural circuits of the barn owl, is used to trigger saccades to acoustic targets in parallel with visual targets. Two different types of learning are also demonstrated on the saccadic system using floating-gate technology allowing the non-volatile storage of analog parameters directly on the chip. Finally, a model of visual attention is used to select and track moving targets against textured backgrounds, driving both saccadic and smooth pursuit eye movements to maintain the image of the target in the center of the field of view. This system represents one of the few efforts in this field to integrate both neuromorphic sensory processing and motor control in a closed-loop fashion.

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Technology scaling has enabled drastic growth in the computational and storage capacity of integrated circuits (ICs). This constant growth drives an increasing demand for high-bandwidth communication between and within ICs. In this dissertation we focus on low-power solutions that address this demand. We divide communication links into three subcategories depending on the communication distance. Each category has a different set of challenges and requirements and is affected by CMOS technology scaling in a different manner. We start with short-range chip-to-chip links for board-level communication. Next we will discuss board-to-board links, which demand a longer communication range. Finally on-chip links with communication ranges of a few millimeters are discussed.

Electrical signaling is a natural choice for chip-to-chip communication due to efficient integration and low cost. IO data rates have increased to the point where electrical signaling is now limited by the channel bandwidth. In order to achieve multi-Gb/s data rates, complex designs that equalize the channel are necessary. In addition, a high level of parallelism is central to sustaining bandwidth growth. Decision feedback equalization (DFE) is one of the most commonly employed techniques to overcome the limited bandwidth problem of the electrical channels. A linear and low-power summer is the central block of a DFE. Conventional approaches employ current-mode techniques to implement the summer, which require high power consumption. In order to achieve low-power operation we propose performing the summation in the charge domain. This approach enables a low-power and compact realization of the DFE as well as crosstalk cancellation. A prototype receiver was fabricated in 45nm SOI CMOS to validate the functionality of the proposed technique and was tested over channels with different levels of loss and coupling. Measurement results show that the receiver can equalize channels with maximum 21dB loss while consuming about 7.5mW from a 1.2V supply. We also introduce a compact, low-power transmitter employing passive equalization. The efficacy of the proposed technique is demonstrated through implementation of a prototype in 65nm CMOS. The design achieves up to 20Gb/s data rate while consuming less than 10mW.

An alternative to electrical signaling is to employ optical signaling for chip-to-chip interconnections, which offers low channel loss and cross-talk while providing high communication bandwidth. In this work we demonstrate the possibility of building compact and low-power optical receivers. A novel RC front-end is proposed that combines dynamic offset modulation and double-sampling techniques to eliminate the need for a short time constant at the input of the receiver. Unlike conventional designs, this receiver does not require a high-gain stage that runs at the data rate, making it suitable for low-power implementations. In addition, it allows time-division multiplexing to support very high data rates. A prototype was implemented in 65nm CMOS and achieved up to 24Gb/s with less than 0.4pJ/b power efficiency per channel. As the proposed design mainly employs digital blocks, it benefits greatly from technology scaling in terms of power and area saving.

As the technology scales, the number of transistors on the chip grows. This necessitates a corresponding increase in the bandwidth of the on-chip wires. In this dissertation, we take a close look at wire scaling and investigate its effect on wire performance metrics. We explore a novel on-chip communication link based on a double-sampling architecture and dynamic offset modulation technique that enables low power consumption and high data rates while achieving high bandwidth density in 28nm CMOS technology. The functionality of the link is demonstrated using different length minimum-pitch on-chip wires. Measurement results show that the link achieves up to 20Gb/s of data rate (12.5Gb/s/$\mu$m) with better than 136fJ/b of power efficiency.

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We report the fabrication of a novel surface-enhanced Raman scattering (SERS) substrate with a controllable enhancement factor (EF) using femtosecond laser direct writing on Ag+-doped phosphate glass followed by chemical plating at similar to 40 degrees C. Silver seeds were first photoreduced using a femtosecond laser in a laser-irradiated area and then transformed into silver nanoparticles of suitable size for SERS application in the subsequent chemical plating. Rhodamine 6G was used as a probing molecule to investigate the enhancement effect of a Raman signal on the substrate. Nearly homogenous enhancement of the Raman signal over the Substrate was achieved, and the EF of the substrate was controlled to some extent by adjusting fabrication parameters. Moreover, the ability of forming a SERS platform in an embedded microfluidic chamber would be of great use for establishing a compact lab-on-a-chip device based on Raman analysis.

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We study the behaviour of atoms in a field with both static magnetic field and radio frequency (rf) magnetic field. We calculate the adiabatic potential of atoms numerically beyond the usually rotating wave approximation, and it is pointed that there is a great difference between using these two methods. We find the preconditions when RWA is valid. In the extreme of static field almost parallel to rf field, we reach an analytic formula. Finally, we apply this method to Rb-87 and propose a guide based on an rf field on atom chip.

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This paper shows that film bulk acoustic resonator (FBAR) arrays can be very useful sensors either to detect physical parameters such as temperature and pressure directly or to detect bio-chemicals with extremely high sensitivities by incorporating a chemisorption layer or bio-probe molecules. Furthermore, it also shows that surface acoustic wave devices can be integrated with a FBAR sensor array on the same piezoelectric substrate as the microfluidics systems to perform transportation and mixing of biosamples etc. demonstrating the possibility to fabricate integrated lab-on-a-chip detection systems, in which all the actuators and sensors are operated by acoustic wave devices. This makes the detection system simple, low cost and easy to operate and hence has great commercial potential. © 2011 Inderscience Enterprises Ltd.

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Bio-inspired designs can provide an answer to engineering problems such as swimming strategies at the micron or nano-scale. Scientists are now designing artificial micro-swimmers that can mimic flagella-powered swimming of micro-organisms. In an application such as lab-on-a-chip in which micro-object manipulation in small flow geometries could be achieved by micro-swimmers, control of the swimming direction becomes an important aspect for retrieval and control of the micro-swimmer. A bio-inspired approach for swimming direction reversal (a flagellum bearing mastigonemes) can be used to design such a system and is being explored in the present work. We analyze the system using a computational framework in which the equations of solid mechanics and fluid dynamics are solved simultaneously. The fluid dynamics of Stokes flow is represented by a 2D Stokeslets approach while the solid mechanics behavior is realized using Euler-Bernoulli beam elements. The working principle of a flagellum bearing mastigonemes can be broken up into two parts: (1) the contribution of the base flagellum and (2) the contribution of mastigonemes, which act like cilia. These contributions are counteractive, and the net motion (velocity and direction) is a superposition of the two. In the present work, we also perform a dimensional analysis to understand the underlying physics associated with the system parameters such as the height of the mastigonemes, the number of mastigonemes, the flagellar wave length and amplitude, the flagellum length, and mastigonemes rigidity. Our results provide fundamental physical insight on the swimming of a flagellum with mastigonemes, and it provides guidelines for the design of artificial flagellar systems.

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In this paper we quantitatively analyse the performance of magnetically-driven artificial cilia for lab-on-a-chip applications. The artificial cilia are fabricated using thin polymer films with embedded magnetic nano-particles and their deformation is studied under different external magnetic fields and flows. A coupled magneto-mechanical solid-fluid model that accurately captures the interaction between the magnetic field, cilia and fluid is used to simulate the cilia motion. The elastic and magnetic properties of the cilia are obtained by fitting the results of the computational model to the experimental data. The performance of the artificial cilia with a non-uniform cross-section is characterised using the numerical model for two channel configurations that are of practical importance: an open-loop and a closed-loop channel. We predict that the flow and pressure head generated by the artificial cilia can be as high as 18 microlitres per minute and 3 mm of water, respectively. We also study the effect of metachronal waves on the flow generated and show that the fluid propelled increases drastically compared to synchronously beating cilia, and is unidirectional. This increase is significant even when the phase difference between adjacent cilia is small. The obtained results provide guidelines for the optimal design of magnetically-driven artificial cilia for microfluidic propulsion.

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New embedded predictive control applications call for more eficient ways of solving quadratic programs (QPs) in order to meet demanding real-time, power and cost requirements. A single precision QP-on-a-chip controller is proposed, implemented in afield-programmable gate array (FPGA) with an iterative linear solver at its core. A novel offline scaling procedure is introduced to aid the convergence of the reduced precision solver. The feasibility of the proposed approach is demonstrated with a real-time hardware-in-the-loop (HIL) experimental setup where an ML605 FPGA board controls a nonlinear model of a Boeing 747 aircraft running on a desktop PC through an Ethernet link. Simulations show that the quality of the closed-loop control and accuracy of individual solutions is competitive with a conventional double precision controller solving linear systems using a Riccati recursion. © 2012 IFAC.

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In this paper, we demonstrate an approach for the local synthesis of ZnO nanowires (ZnO NWs) and the potential for such structures to be incorporated into device applications. Three network ZnO NW devices are fabricated on a chip by using a bottom-up synthesis approach. Microheaters (defined by standard semiconductor processing) are used to synthesize the ZnO NWs under a zinc nitrate (Zn(NO3)2·6H2O) and hexamethylenetetramine (HMTA, (CH2)6·N4) solution. By controlling synthesis parameters, varying densities of networked ZnO NWs are locally synthesized on the chip. The fabricated networked ZnO NW devices are then characterized using UV excitation and cyclic voltammetry (CV) experiments to measure their photoresponse and electrochemical properties. The experimental results show that the techniques and material systems presented here have the potential to address interesting device applications using fabrication methods that are fully compatible with standard semiconductor processing. © 2013 IEEE.

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Scalable and cost effective patterning of polymer structures and their surface textures is essential to engineer material properties such as liquid wetting and dry adhesion, and to design artificial biological interfaces. Further, fabrication of high-aspect-ratio microstructures often requires controlled deep-etching methods or high-intensity exposure. We demonstrate that carbon nanotube (CNT) composites can be used as master molds for fabrication of high-aspect-ratio polymer microstructures having anisotropic nanoscale textures. The master molds are made by growth of vertically aligned CNT patterns, capillary densification of the CNTs using organic solvents, and capillary-driven infiltration of the CNT structures with SU-8. The composite master structures are then replicated in SU-8 using standard PDMS transfer molding methods. By this process, we fabricated a library of replicas including vertical micro-pillars, honeycomb lattices with sub-micron wall thickness and aspect ratios exceeding 50:1, and microwells with sloped sidewalls. This process enables batch manufacturing of polymer features that capture complex nanoscale shapes and textures, while requiring only optical lithography and conventional thermal processing. © 2011 The Royal Society of Chemistry.

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Alternative and more efficient computational methods can extend the applicability of model predictive control (MPC) to systems with tight real-time requirements. This paper presents a system-on-a-chip MPC system, implemented on a field-programmable gate array (FPGA), consisting of a sparse structure-exploiting primal dual interior point (PDIP) quadratic program (QP) solver for MPC reference tracking and a fast gradient QP solver for steady-state target calculation. A parallel reduced precision iterative solver is used to accelerate the solution of the set of linear equations forming the computational bottleneck of the PDIP algorithm. A numerical study of the effect of reducing the number of iterations highlights the effectiveness of the approach. The system is demonstrated with an FPGA-in-the-loop testbench controlling a nonlinear simulation of a large airliner. This paper considers many more manipulated inputs than any previous FPGA-based MPC implementation to date, yet the implementation comfortably fits into a midrange FPGA, and the controller compares well in terms of solution quality and latency to state-of-the-art QP solvers running on a standard PC. © 1993-2012 IEEE.