一种FPGA的嵌入式可重构机器人控制系统

提出一种基于FPGA的可重构嵌入式微处理器控制系统.在FPGA中嵌入两个NiosⅡ软核,用VHDL语言编写用户自定义组件.在一个由NiosⅡ软核组成的处理器上实现PWM信号生成、编码器信号处理以及多电机同步伺服运算等,在另一个处理器实现机器人任务管理.该控制系统针对微小型爬壁机器人的控制系统设计,不仅具有良好的实时多任务处理能力,而且具有可重构的特点,因而可应用于一类微小型机器人控制系统以提高其设计的灵活性.

FPGA在偏振耦合测试仪中的应用

在偏振耦合测试仪的PCI接口数据采集系统中,现场可编程门阵列(FieldProgramableGateArray)实现了对模/数器件的控制功能,同时完成了与PCI总线控制器间的数据接口功能。应用自顶向下的设计思想,完成了FPGA内部的逻辑设计,并对其逻辑功能进行了仿真验证,给出了FPGA数据采集时的测试时序图。应用FPGA实现的数据采集系统可以检测出偏振耦合检测仪中的微弱干涉光信号。

基于FPGA高速并行FFT处理器设计与实现

在研究快速傅里叶变换(FFT)算法的基础上,根据FPGA性能高、灵活性强、速度快的特点,提出了高效的基4-FFT处理器的实现方法。数据存储采用分块存储的方法,大大提高了存取速度。数据寻址采用新型的地址产生方法,可并行产生所需数据地址。同时,在蝶形单元的设计中很好的将并行运算技术和流水线技术相结合了起来,又进一步提高了运算速度。测试结果表明,时钟在50MHz时完成1024点FFT的时间为25.6μs,满足了应用实时性的要求。

基于DSP和FPGA的火腿肠质量检测系统设计

本文研究的主要内容为基于DSP和FPGA的火腿肠质量检测系统设计。论文首先介绍了研究背景及意义和火腿肠质量检测系统原理，接着介绍了传统的专用和通用图像处理系统的结构、特点和模型，并通过分析DSP芯片以及DSP系统的特点，提出了基于DSP和FPGA芯片的实时图像处理系统。该系统不同于传统基于PC机模式的图像处理系统，发挥了DSP和FPGA两者的优势，能更好地提高图像处理系统实时性能。 其次,论述了以TMS320C6416 DSP为核心处理器实时图像处理系统的设计原理与组成，对系统主要部分的电路设计进行了详细的介绍，研究分析了高速电路设计中的几个关键问题。对系统进行了软件开发与调试，包括DSP程序设计和FPGA模块设计，并给出了FPGA各个模块仿真调试结果。经系统调试与实验验证，系统工作稳定可靠,拥有很高的实时性。 最后, 在火腿肠质量检测的图像算法中，对火腿肠的鼓泡问题进行了分析和相关算法的设计。首先实现了FPGA的图像预处理，将流水线处理技术和并行处理等技术应用到电路设计中，提高了处理速度，节省了硬件开销。在DSP中采用了多种算法对火腿肠图像进行了进一步的处理，使其特征更为明显。结果表明，实现的硬件电路能够满足系统功能和处理时间要求，同时有比较高的识别率，具有一定的参考价值。

Progettazione e sintesi di nuovi antagonisti CB1 a struttura pirazolica come potenziali radiofarmaci per la PET imaging

Cannabinoid receptors are members of the large family of G-protein coupled receptors. Two types of cannabinoid receptor have been discovered: CB1 and CB2. CB1 receptors are localised predominantly in the brain whereas CB2 receptors are more abundant in peripheral nervous system cells. CB1 receptors have been related with a number of disorders, including depression, anxiety, stress, schizophrenia, chronic pain and obesity. For this reason, several cannabinoid ligands were developed as drug candidates. Among these ligands, a prominent position is occupied by SR141716 (Rimonabant), which is a pyrazole derivative with inverse agonist activity discovered by Sanofi-Synthelabo in 1994. This compound was marketed in Europe as an anti-obesity drug, but subsequently withdrawn due to its side-effects. Since the relationship between the CB1 receptors’ functional modification, density and distribution, and the beginning of a pathological state is still not well understood, the development of radio-ligands suitable for in vivo PET (Positron Emission Tomography) functional imaging of CB1 receptors remains an important area of research in medicine and drug development. To date, a few radiotracers have been synthesised and tested in vivo, but most of them afforded unsatisfactory brain imaging results. A handful of radiolabelled CB1 PET ligands have also been submitted to clinical trials in humans. In this PhD Thesis the design, synthesis and characterization of three new classes of potential high-affinity CB1 ligands as candidate PET tracers is described.

Una breve sintesi sulla presenza degli anglicismi nel settore delle lingue speciali riguardo all 'italiano contemporaneo

This article presents the classification and description of borrowings from the English language in the sector of special languages with reference to contemporary Italian. The present times are characterized by multiplicity of linguistic variants. Different, ready-made solutions to are observed this complex situation.

Efficient FPGA Hardware Development: A Multi-Language Approach

This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of different hardware languages in a way that harnesses the best features of each language. This is illustrated in this paper by the integration of two hardware languages in the form of HIDE: a structured hardware language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog, and Handel-C: an ANSI C-like hardware language which allows software and hardware engineers alike to target FPGAs from high-level algorithmic descriptions. On the one hand, HIDE has proven to be very successful in the description and generation of highly optimised parameterisable FPGA circuits from geometric descriptions. On the other hand, Handel-C has also proven to be very successful in the rapid design and prototyping of FPGA circuits from algorithmic application descriptions. The proposed integrated framework hence harnesses HIDE for the generation of highly optimised circuits for regular parts of algorithms, while Handel-C is used as a top-level design language from which HIDE functionality is dynamically invoked. The overall message of this paper posits that there need not be an exclusive choice between different hardware design flows. Rather, an integrated framework where different design flows can seamlessly interoperate should be adopted. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware languages.

Multidimensional DSP Core Synthesis for FPGA

This paper, chosen as a best paper from the 2004 SAMOS Workshop on Computer Systems: describes a novel, efficient methodology for automatically creating embedded DSP computer systems. The novelty arises since now embedded electronic signal processing systems, such as radar or sonar, can be designed by anyone from the algorithm level, i.e. no low level system design experience is required, whilst still achieving low controllable implementation overheads and high real time performance. In the chosen design example, a bank of Normalised Lattice Filter (NLF) components is created which a four-fold reduction in the required processing resource with no performance decrease.

Rapid Implementation and Optimisation of DSP Systems on FPGA-Centric Hetrogeneous Platforms

This paper, chosen as a best paper from the 2005 SAMOS Workshop on Computer Systems: describes the for the first time the major Abhainn project for automated system level design of embedded signal processing systems. In particular, this describes four key novelties: novel algorithm modelling techniques for DSP systems, automated implementation realisation, algorithm transformation for system optimisation and automated inter-processor communication. This is applied to two complex systems: a radar and sonar system. In both cases technology which allows non-experts to automatically create low-overhead, high performance embedded signal processing systems is exhibited.