Testing of Interposer-Based 2.5D Integrated Circuits

The unprecedented and relentless growth in the electronics industry is feeding the demand for integrated circuits (ICs) with increasing functionality and performance at minimum cost and power consumption. As predicted by Moore's law, ICs are being aggressively scaled to meet this demand. While the continuous scaling of process technology is reducing gate delays, the performance of ICs is being increasingly dominated by interconnect delays. In an effort to improve submicrometer interconnect performance, to increase packing density, and to reduce chip area and power consumption, the semiconductor industry is focusing on three-dimensional (3D) integration. However, volume production and commercial exploitation of 3D integration are not feasible yet due to significant technical hurdles.

At the present time, interposer-based 2.5D integration is emerging as a precursor to stacked 3D integration. All the dies and the interposer in a 2.5D IC must be adequately tested for product qualification. However, since the structure of 2.5D ICs is different from the traditional 2D ICs, new challenges have emerged: (1) pre-bond interposer testing, (2) lack of test access, (3) limited ability for at-speed testing, (4) high density I/O ports and interconnects, (5) reduced number of test pins, and (6) high power consumption. This research targets the above challenges and effective solutions have been developed to test both dies and the interposer.

The dissertation first introduces the basic concepts of 3D ICs and 2.5D ICs. Prior work on testing of 2.5D ICs is studied. An efficient method is presented to locate defects in a passive interposer before stacking. The proposed test architecture uses e-fuses that can be programmed to connect or disconnect functional paths inside the interposer. The concept of a die footprint is utilized for interconnect testing, and the overall assembly and test flow is described. Moreover, the concept of weighted critical area is defined and utilized to reduce test time. In order to fully determine the location of each e-fuse and the order of functional interconnects in a test path, we also present a test-path design algorithm. The proposed algorithm can generate all test paths for interconnect testing.

In order to test for opens, shorts, and interconnect delay defects in the interposer, a test architecture is proposed that is fully compatible with the IEEE 1149.1 standard and relies on an enhancement of the standard test access port (TAP) controller. To reduce test cost, a test-path design and scheduling technique is also presented that minimizes a composite cost function based on test time and the design-for-test (DfT) overhead in terms of additional through silicon vias (TSVs) and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a test path.

To address the scenario of high density of I/O ports and interconnects, an efficient built-in self-test (BIST) technique is presented that targets the dies and the interposer interconnects. The proposed BIST architecture can be enabled by the standard TAP controller in the IEEE 1149.1 standard. The area overhead introduced by this BIST architecture is negligible; it includes two simple BIST controllers, a linear-feedback-shift-register (LFSR), a multiple-input-signature-register (MISR), and some extensions to the boundary-scan cells in the dies on the interposer. With these extensions, all boundary-scan cells can be used for self-configuration and self-diagnosis during interconnect testing. To reduce the overall test cost, a test scheduling and optimization technique under power constraints is described.

In order to accomplish testing with a small number test pins, the dissertation presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an system on chip (SoC) die on the interposer while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group.

Finally, the dissertation presents a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs. An SoC die in the 2.5D IC is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated.

In summary, the dissertation targets important design and optimization problems related to testing of interposer-based 2.5D ICs. The proposed research has led to theoretical insights, experiment results, and a set of test and design-for-test methods to make testing effective and feasible from a cost perspective.

High-Performance WSe2 CMOS Technology and Integrated Circuits.

Because of their extraordinary structural and electrical properties, two dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (~38) and small static power (Pico-Watts), paving the way for low power electronic system in 2D materials.

Introduction to the Special Issue on Biomedical and Bioelectronic Circuits for Enhanced Diagnosis and Therapy

The 22 papers in this special issue focus on biomedical and biolectronic circuits for enhanced diagnosis and therapy.

Energy efficient measures to reduce electrical energy use in commercial buildings in New York City

GEA Consulting Engineers, acting as the design engineers, was hired by the owner, East Village 207 Residential LLC2 for energy modeling for compliance with LEED NC V3 -- This report details the results of the energy simulation done with the 100% construction documents -- This report only refers to entities within the LEED3 project boundary -- The project consists of a new eight-story high-end residential condominium building with 81 units, as shown in illustration 1, and approximately 117,905 GSF, equivalent to 10,953.73 m2, is located at 211 E 13th Street in New York, NY -- The residential portion of the building will function 24-7 -- The design goal is to utilize energy efficient measures to reduce electrical energy use and aims to achieve LEED certification -- LEED EA Credit 14 requires a building to demonstrate a percentage improvement in the proposed building performance compared with the baseline building -- The Credit rewards 1 point for achieving 12% reduction in energy costs -- Additionally, the Credit rewards another point for each subsequent reduction of 2% in the building’s energy cost

Electrical AC behaviour of MPCVD diamond Schottky diodes

The present work reports some experimental results on the electrical AC behaviour of metal-undoped diamond Schottky diodes fabricated with a free-standing MPCVD diamond film (5 mum thick). The metals are gold for the ohmic contact and aluminium for the rectifier. The capacitance and loss tangent vs, frequency shows that capacitance presents a relaxation maximum at frequencies near 10 kHz at room temperature. Although the simple model (small equivalent circuit) can justify the values for the relaxation, it cannot justify the departure from the Debye model, also verified in the Cole-Cole plot. Taking into account the existence of traps in the depletion region, a best fit to the experimental results was obtained. The difference between the Fermi level and the band edge of 0.2-0.3 eV is in agreement with the activation energy found from the loss tangent analysis. The capacitance with applied voltage (Mott-Schottky plots) gives a defect density of 10(16) cm(-3) with contact potentials near 0.5 V and the profile of defect density obtained shows a major density (approx. 10(17) cm(-3)) in a layer with a thickness less than 50 nm from the junction, decreasing by one order of magnitude with increasing distance. Finally a structural model is proposed to explain the AC behaviour found. (C) 2001 Elsevier Science B.V. All rights reserved.

Photonic packaging: transforming silicon photonic integrated circuits into photonic devices

Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.

A Comparative Analysis Between Genetic Algorithms and Complex Nonlinear Least Squares on Electrical Impedance Characterization

This paper compares the performance of the complex nonlinear least squares algorithm implemented in the LEVM/LEVMW software with the performance of a genetic algorithm in the characterization of an electrical impedance of known topology. The effect of the number of measured frequency points and of measurement uncertainty on the estimation of circuit parameters is presented. The analysis is performed on the equivalent circuit impedance of a humidity sensor.

Engagement of multifocal neural circuits during recall of autobiographical happy events

Happy emotional states have not been extensively explored in functional magnetic resonance imaging studies using autobiographic recall paradigms. We investigated the brain circuitry engaged during induction of happiness by standardized script-driven autobiographical recall in 11 healthy subjects (6 males), aged 32.4 ± 7.2 years, without physical or psychiatric disorders, selected according to their ability to vividly recall personal experiences. Blood oxygen level-dependent (BOLD) changes were recorded during auditory presentation of personal scripts of happiness, neutral content and negative emotional content (irritability). The same uniform structure was used for the cueing narratives of both emotionally salient and neutral conditions, in order to decrease the variability of findings. In the happiness relative to the neutral condition, there was an increased BOLD signal in the left dorsal prefrontal cortex and anterior insula, thalamus bilaterally, left hypothalamus, left anterior cingulate gyrus, and midportions of the left middle temporal gyrus (P < 0.05, corrected for multiple comparisons). Relative to the irritability condition, the happiness condition showed increased activity in the left insula, thalamus and hypothalamus, and in anterior and midportions of the inferior and middle temporal gyri bilaterally (P < 0.05, corrected), varying in size between 13 and 64 voxels. Findings of happiness-related increased activity in prefrontal and subcortical regions extend the results of previous functional imaging studies of autobiographical recall. The BOLD signal changes identified reflect general aspects of emotional processing, emotional control, and the processing of sensory and bodily signals associated with internally generated feelings of happiness. These results reinforce the notion that happiness induction engages a wide network of brain regions.

A física do violino

Neste artigo apresentamos uma descrição geral da física do violino, analisando os conceitos que lhes dão sustentação física e que revelam toda a riqueza e o potencial pedagógico do assunto. Destacamos as contribuições de físicos como Helmholtz, Savart, Raman e Saunders no esforço para descrever a vibração produzida pelo arco nas cordas, e por compreender as propriedades acústicas do instrumento. Descrevemos a função de cada uma das componentes do instrumento e discutimos a importância dos modos normais de vibração dos tampos e do cavalete na resposta acústica do violino. A ressonância acústica da caixa do violino (ressonância de Helmholtz) será discutida fazendo-se um paralelo entre osciladores mecânico, elétrico e acústico. Discutiremos a resposta acústica do violino e descreveremos a produção de seu som caraterístico, que resulta da forma de onda originada pela excitação das cordas pelo arco, influenciada pelas vibrações e ressonâncias do corpo do violino, seus tampos e o cavalete.

Per capita versus adult-equivalent estimates of calorie availability in household budget surveys

This study aims to estimate an adult-equivalent scale for calorie requirements and to determine the differences between adult-equivalent and per capita measurements of calorie availability in the Brazilian population. The study used data from the 2002-2003 Brazilian Household Budget Survey. The calorie requirement for a reference adult individual was based on the mean requirements for adult males and females (2,550kcal/day). The conversion factors were defined as the ratios between the calorie requirements for each age group and gender and that of the reference adult. The adult-equivalent calorie availability levels were higher than the per capita levels, with the largest differences in rural and low-income households. Differences in household calorie availability varied from 22kcal/day (households with adults and an adolescent) to 428kcal/day (households with elderly individuals), thus showing that per capital measurements can underestimate the real calorie availability, since they overlook differences in household composition.

Electrical transport in single-crystalline Li(0.9)Mo(6)O(17): A two-band Luttinger liquid exhibiting Bose metal behavior

Temperature-dependent electrical resistance in quasi-one-dimensional Li(0.9)Mo(6)O(17) is described by two Luttinger liquid anomalous exponents alpha, each associated with a distinct one dimensional band. The band with alpha < 1 is argued to crossover to a higher dimension below the temperature T(M'), leading to superconductivity. Disorder and magnetic fields are shown to induce the Bose metal behavior in this bulk compound.

Diffusive Synchronization of Hyperchaotic Lorenz Systems

The synchronizing properties of two diffusively coupled hyperchaotic Lorenz 4D systems are investigated by calculating the transverse Lyapunov exponents and by observing the phase space trajectories near the synchronization hyperplane. The effect of parameter mismatch is also observed. A simple electrical circuit described by the Lorenz 4D equations is proposed. Some results from laboratory experiments with two coupled circuits are presented. Copyright (C) 2009 Ruy Barboza.

Evolution of magnetic properties and crystallographic texture in electrical steel with large plastic deformation

Deformation leads to a hardening of steel due to an increase in the density of dislocations and a reduction in their mobility, giving rise to a state of elevated residual stresses in the crystal lattice. In the microstructure, one observes an increase in the contribution of crystalline orientations which are unfavorable to the magnetization, as seen, for example, by a decrease in B(50), the magnetic flux density at a field of 50 A/cm. The present study was carried out with longitudinal strips of fully processed non-oriented (NO) electrical steel, with deformations up to 70% resulting from cold rolling in the longitudinal direction. With increasing plastic deformation, the value of B(50) gradually decreases until it reaches a minimum value, where it remains even for larger deformations. On the other hand, the coercive field H(c) continually increases. Magnetometry results and electron backscatter diffraction results are compared and discussed. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3560895]