Fatores de transcrição reguladores do metabolismo do glicogênio em Neurospora crassa: caracterização parcial e identificação de alvos de ligação por ChIP-Seq

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Método de inversão matricial rápido GSGR para vectoring em sistemas xDSL, com implementação em chip DSP

Este trabalho apresenta um método rápido de inversão de matrizes densas, e uma possível aplicação com métodos de Vectoring, em pré-codificação e cancelamento de crosstalk de sistemas xDSL. A família de tecnologias xDSL utiliza os pares trançados de fios de cobre telefônicos como meio físico para transmitir dados digitais. O crosstalk é a principal causa de degradação de sinais na mais nova geração de sistemas xDSL, o G.fast, e para combatê-lo são utilizadas técnicas de pré-codificação e cancelamento, chamadas de Vectoring. O método proposto, chamado de GSGR, consiste em uma abordagem diferente para o método clássico de Squared Givens Rotations (SGR), adequado a implementações em plataformas embarcadas de processamento digital de sinais. Foram realizados testes comparativos do método GSGR com métodos diretos clássicos de inversão, utilizando uma plataforma digital multicore baseada no chip TI DSP TMS320C6670 e a plataforma de software Matlab. Os resultados dos testes de inversão de matrizes usando dados reais e dados simulados mostraram que o GSGR foi superior em velocidade de execução sem apresentar perdas significativas de acurácia para a aplicação em sistemas xDSL.

Linkage disequilibrium levels in Bos indicus and Bos taurus cattle using medium and high density SNP chip data and different minor allele frequency distributions

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

ChIP-seq reveals a role for CrzA in the Aspergillus fumigatus high-osmolarity glycerol response (HOG) signalling pathway

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Dispositivo microfluídico de borracha natural (LAB-ON-A-CHIP)

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

A flexible lab-on-a-chip for the synthesis and magnetic separation of magnetite decorated with gold nanoparticles

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Natural formations at the Earth-Moon triangular point in perturbed restricted problems

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Luminescence properties of Eu-complex formations into ordered mesoporous silica particles obtained by the spray pyrolysis process

Ordered mesoporous, highly luminescent SiO2 particles have been synthesized by spray pyrolysis from solutions containing tetraethylorthosilicate (TEOS), Eu(NO3)3.6H2O, and cetyltrimethylammonium bromide (CTAB) as structure-directing agents. The 1,10-phenantroline (Phen) molecules were coordinated in a post-synthesis step by a simple wet impregnation method. In addition, other matrices were also prepared by the encapsulation of europium complex Eu(fod)3 (where fod = 6,6,7,7,8,8,8-heptafluoro-2,2-dimethyl-3,5-octanedionato) into mesoporous silica, and then the Phen molecules were encapsulated by different impregnation steps, after which the luminescence properties were investigated. The obtained materials were characterized by scanning electron microscopy (SEM), transmission electron microscopy (TEM), powder x-ray diffraction (XRD) and Fourier transform infrared (FTIR) spectroscopy. Powders with polydisperse spherical grains were obtained, displaying an ordered hexagonal array of mesochannels. Luminescence results revealed that Phen molecules had been successfully coordinated as an additional ligand in the Eu(fod)3 complex into the channels of the mesoporous particles without disrupting the structure.

Thermal analysis of the chip formation in austenitic stainless steel

The most important property of austenitic stainless steels is corrosion resistance. In these steels, the transition between paramagnetic and ferromagnetic conditions occurs at low temperatures. Therefore, the use of austenitic stainless steels in conditions in which ferromagnetism absence is important can be considered. On the other hand, the formation of strain-induced martensite is detected when austenitic stainless steels are deformed as well as machined. The strain-induced martensite formed especially in the machining process is not uniform through the chip and its formation can also be related to the Md temperature. Therefore, both the temperature distribution and the gradient during the cutting and chip formation are important to identify regions in which martensite formation is propitiated. The main objective here is evaluate the strain-induced martensite formation throughout machining by observing microstructural features and comparing these to thermal results obtained through finite element method analysis. Results show that thermal analysis can give support to the martensite identified in the microstructural analysis.

CMoS lab-on-a-chip devices for individual cell biology

The development of microlectronic lab-on-a-chip devices (LOACs) can now be pursued thanks to the continous advances in silicon technology. LOACs are miniaturized devices whose aim is to perform in a more efficient way specific chemical or biological analysis protocols which are usually carried out with traditional laboratory equipment. In this application area, CMOS technology has the potential to integrate LOAC functionalities for cell biology applications in single chips, e.g. sensors, actuators, signal conditioning and processing circuits. In this work, after a review of the state of the art, the development of a CMOS prototype chip for individual cell manipulation and detection based on dielectrophoresis will be presented. Issues related to the embedded optical and capacitive detection of cells will be discussed together with the main experimental results obtained in manipulation and detection of living cells and microparticles.

Lab-on-a-chip: the future in water quality detection

Interpretación realizada por las alumnas en prácticas de la Facultad de Traducción e Interpretación, Estíbaliz López-Leiton Trujillo, Danaide Rodríguez Hernández, Esther Ramírez Millares.

Tecniche per il controllo dinamico del consumo di potenza per piattaforme system-on-chip

Providing support for multimedia applications on low-power mobile devices remains a significant research challenge. This is primarily due to two reasons: • Portable mobile devices have modest sizes and weights, and therefore inadequate resources, low CPU processing power, reduced display capabilities, limited memory and battery lifetimes as compared to desktop and laptop systems. • On the other hand, multimedia applications tend to have distinctive QoS and processing requirementswhichmake themextremely resource-demanding. This innate conflict introduces key research challenges in the design of multimedia applications and device-level power optimization. Energy efficiency in this kind of platforms can be achieved only via a synergistic hardware and software approach. In fact, while System-on-Chips are more and more programmable thus providing functional flexibility, hardwareonly power reduction techniques cannot maintain consumption under acceptable bounds. It is well understood both in research and industry that system configuration andmanagement cannot be controlled efficiently only relying on low-level firmware and hardware drivers. In fact, at this level there is lack of information about user application activity and consequently about the impact of power management decision on QoS. Even though operating system support and integration is a requirement for effective performance and energy management, more effective and QoSsensitive power management is possible if power awareness and hardware configuration control strategies are tightly integratedwith domain-specificmiddleware services. The main objective of this PhD research has been the exploration and the integration of amiddleware-centric energymanagement with applications and operating-system. We choose to focus on the CPU-memory and the video subsystems, since they are the most power-hungry components of an embedded system. A second main objective has been the definition and implementation of software facilities (like toolkits, API, and run-time engines) in order to improve programmability and performance efficiency of such platforms. Enhancing energy efficiency and programmability ofmodernMulti-Processor System-on-Chips (MPSoCs) Consumer applications are characterized by tight time-to-market constraints and extreme cost sensitivity. The software that runs on modern embedded systems must be high performance, real time, and even more important low power. Although much progress has been made on these problems, much remains to be done. Multi-processor System-on-Chip (MPSoC) are increasingly popular platforms for high performance embedded applications. This leads to interesting challenges in software development since efficient software development is a major issue for MPSoc designers. An important step in deploying applications on multiprocessors is to allocate and schedule concurrent tasks to the processing and communication resources of the platform. The problem of allocating and scheduling precedenceconstrained tasks on processors in a distributed real-time system is NP-hard. There is a clear need for deployment technology that addresses thesemulti processing issues. This problem can be tackled by means of specific middleware which takes care of allocating and scheduling tasks on the different processing elements and which tries also to optimize the power consumption of the entire multiprocessor platform. This dissertation is an attempt to develop insight into efficient, flexible and optimalmethods for allocating and scheduling concurrent applications tomultiprocessor architectures. It is a well-known problem in literature: this kind of optimization problems are very complex even in much simplified variants, therefore most authors propose simplified models and heuristic approaches to solve it in reasonable time. Model simplification is often achieved by abstracting away platform implementation ”details”. As a result, optimization problems become more tractable, even reaching polynomial time complexity. Unfortunately, this approach creates an abstraction gap between the optimization model and the real HW-SW platform. The main issue with heuristic or, more in general, with incomplete search is that they introduce an optimality gap of unknown size. They provide very limited or no information on the distance between the best computed solution and the optimal one. The goal of this work is to address both abstraction and optimality gaps, formulating accurate models which accounts for a number of ”non-idealities” in real-life hardware platforms, developing novel mapping algorithms that deterministically find optimal solutions, and implementing software infrastructures required by developers to deploy applications for the targetMPSoC platforms. Energy Efficient LCDBacklightAutoregulation on Real-LifeMultimediaAp- plication Processor Despite the ever increasing advances in Liquid Crystal Display’s (LCD) technology, their power consumption is still one of the major limitations to the battery life of mobile appliances such as smart phones, portable media players, gaming and navigation devices. There is a clear trend towards the increase of LCD size to exploit the multimedia capabilities of portable devices that can receive and render high definition video and pictures. Multimedia applications running on these devices require LCD screen sizes of 2.2 to 3.5 inches andmore to display video sequences and pictures with the required quality. LCD power consumption is dependent on the backlight and pixel matrix driving circuits and is typically proportional to the panel area. As a result, the contribution is also likely to be considerable in future mobile appliances. To address this issue, companies are proposing low power technologies suitable for mobile applications supporting low power states and image control techniques. On the research side, several power saving schemes and algorithms can be found in literature. Some of them exploit software-only techniques to change the image content to reduce the power associated with the crystal polarization, some others are aimed at decreasing the backlight level while compensating the luminance reduction by compensating the user perceived quality degradation using pixel-by-pixel image processing algorithms. The major limitation of these techniques is that they rely on the CPU to perform pixel-based manipulations and their impact on CPU utilization and power consumption has not been assessed. This PhDdissertation shows an alternative approach that exploits in a smart and efficient way the hardware image processing unit almost integrated in every current multimedia application processors to implement a hardware assisted image compensation that allows dynamic scaling of the backlight with a negligible impact on QoS. The proposed approach overcomes CPU-intensive techniques by saving system power without requiring either a dedicated display technology or hardware modification. Thesis Overview The remainder of the thesis is organized as follows. The first part is focused on enhancing energy efficiency and programmability of modern Multi-Processor System-on-Chips (MPSoCs). Chapter 2 gives an overview about architectural trends in embedded systems, illustrating the principal features of new technologies and the key challenges still open. Chapter 3 presents a QoS-driven methodology for optimal allocation and frequency selection for MPSoCs. The methodology is based on functional simulation and full system power estimation. Chapter 4 targets allocation and scheduling of pipelined stream-oriented applications on top of distributed memory architectures with messaging support. We tackled the complexity of the problem by means of decomposition and no-good generation, and prove the increased computational efficiency of this approach with respect to traditional ones. Chapter 5 presents a cooperative framework to solve the allocation, scheduling and voltage/frequency selection problem to optimality for energyefficient MPSoCs, while in Chapter 6 applications with conditional task graph are taken into account. Finally Chapter 7 proposes a complete framework, called Cellflow, to help programmers in efficient software implementation on a real architecture, the Cell Broadband Engine processor. The second part is focused on energy efficient software techniques for LCD displays. Chapter 8 gives an overview about portable device display technologies, illustrating the principal features of LCD video systems and the key challenges still open. Chapter 9 shows several energy efficient software techniques present in literature, while Chapter 10 illustrates in details our method for saving significant power in an LCD panel. Finally, conclusions are drawn, reporting the main research contributions that have been discussed throughout this dissertation.